Digital Transmission
Key Learning Points
• Fundamentals of Voice Digitization
• Pulse Code Modulation
• Quantification Noise
• Multiplexed Digital Lines
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2.5.2 Digital Leased Circuits (from public carriers)
- supports high level of inter-site traffic, generally more
expensive than modem based service
- provides direct digital connection between DTE’s
- basis of most private data & voice networks
 goal: understand organization & capacity of digital networks
Digital switching & transmission for voice & data used in most
public carrier networks
• Eliminates Need for Modem – Voice data must be ‘digitized’
• ISDN: Network that allows Transmission of voice & data
• Public Carriers leased digital circuit rates from kbps..100’sMbps
- digital circuits must co-exist with other circuits for inter-change
traffic
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Amplitude
Voice Digitization
• Voice signals are inherently analog
• Spectral Content of Voice  4000Hz (except )
• Requires Analog To Digital Signal Conversion (ADC)
0
T
2T
3T
4T
5T
Nyquist Sampling Theorem:
- Must Sample Twice Highest Frequency Component
- Sample Rate for Analog Voice Signal = 8000Hz
- Sampling Interval for Voice Signal = 0.125 ms
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(1) Pulse Amplitude Modulation (PAM):
• Analog Voice Signal Sampled  converted to pulse stream
• Pulse Amplitude: discrete analog signal, amplitude =
continuous analog signal
(2) Pulse Code Modulation (PCM): Quantize each Pulse into
Binary Form
- 8 bits used to quantize pulse  range = 0..256 levels
- R = 8 bits * 8000Hz = 64kbps per voice channel
- minimum unit of capacity available for lease
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Analog Voice
Signal
PAM
sample signal
clock
sampling
circuit
Quantizer &
Compander
PCM
Signal
Digital Voice
Signal
10001010 10111010
sample clock
125 us
PAM signal
PCM signal
8 bits
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q = quantization interval: signal (voltage) difference between
adjacent discrete signal levels
- accuracy determined by number of bits in signal: n bits  2n
levels
- signals within a level are represented by same binary codeword
- one bit may be used for signal polarity (+ or - )
analog
voltage range
e.g. n = 3  8 levels
6..8 volts
range  8volts (16 volts)
4..6 volts
interval q = 16/8 = 2 volts
2..4 volts
0..2 volts
0..-2volts
-2..-4 volts
-4..-6 volts
-6..-8volts
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binary
codeword
0 11
0 10
0 01
0 00
1 00
1 01
1 10
1 11
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Each codeword corresponds to nominal input voltage centered at q
• actual input may differ by q/2
• quantization error, , actual signal amplitude – quantized signal
amplitude
• quantization noise: random quantization error variance between
samples
V 0 11

q
0 10
0 01
0 00
1 00
1 01
1 10
-V 1 11
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+q/2
-
0

actual amplitude
 = quantization error
-q/2
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e.g. analog voltage range =  8 volts, n = 3
• 8 signal levels  q = 2 volts
• smaller amplitudes more sensitive to 
• ear is sensitive to noise on quiet, low amplitude speech signals
analog discrete
voltage voltage
6..8
7
4..6
5
2..4
3
0..2
1
0..-2
-1
-2..-4
-3
-4..-6
-5
-6..-8
-7
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
1
1
1
1
1
1
1
1
% maximum
error
14%
20%
33%
100%
100%
33%
20%
14%
binary
codeword
011
010
001
000
100
101
110
111
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Practically non-linear PCM used to overcome quantization noise
• 2 level digitization: segment level and quantization level
• range of input signal amplitudes associated with each quantization
interval
• input signal amplitude increases  corresponding code words
represent larger signal range
Compression and Expansion
•continuous analog signal passed into compressor then into A/D
•expander reverses the operation performed at output of D/A
vi
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compressor
A/D
Network
D/A
expander
vo
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At transmitter: analog voice non-linearly encoded into binary data
1. compressor stage: analog input signal compressed
- encoded value depends on segment level
2.ADC stage: compressed analog signal is digitized &linearly
quantized
At receiver codewords converted to analog voice signal
1. DAC stage: compressed digital signal is linearly converted to
analog signal
2. expander stage: analog output passed through expander –
reverses compressor operation
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e.g. Let Signal Range ± 30 volts and n = 5 bits
32 total levels divided into
• 1 polarity level
• 2 segment levels
• 2 quantum levels
signal
7 < S  15
3<S7
1<S3
0 S1
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polarity segment segment quantam q

code
size
code
1
11
8V
00-11 2
1
1
10
4V
00-11 1
0.5
1
01
2V
00-11 0.5 0.25
1
00
1V
00-11 0.25 0.125
%
12.5
12.5
12.5
12.5
12
• ‘+’ signal encoding polarity segment quantam input range
level
level
• similar for ‘-’signal
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1
11
1
10
1
01
1
00
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
14.0-16.0
12.0-14.0
10.0-12.0
8.00-10.00
6.50-8.00
5.50-6.50
4.50-5.50
3.50-4.50
2.75-3.50
2.25-2.75
1.75-2.25
1.25-1.75
0.875-1.25
0.625-0.875
0.375-0.625
0.00-0.375
output
range
15
13
11
9
7
6
5
4
3.0
2.5
2.0
1.5
1.0
0.75
0.50
0.25
13
polarity segment levels
bit 11
10
1
01
00
-V
-16
00
0
01
-8
-4 -2
2 4
8
16 V
quantum levels
10
11
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PCM codecs (coder/decoder)
• older codecs operated as above
• newer codecs use 2 digital compression/expansion techniques
u-law: (N. America, Japan)
A-law: (ITU-T)
- similar in principal to companding-expansion
- conversion needed when using leased & switched circuits that
span continents
- necessary only for voice
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Multiplexing (MUX)
Link Exchange Circuits: T1, T3, E1…
- carry multiple calls concurrently
- TDM Used: multiple digital signals assigned time slices
voice data: 8 bit sample @ 125us = 64kbps/ voice channel
control overhead:
(i) start of frame (frame synchronization)
(ii) call set-up (signaling)
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DS1 or T1 Links:
• 24 voice channels grouped  1.536Mbps (North America)
• (1 frame/125us  24 slots) = 192 bits/125 us
• 192 bits + 1 framing bit = 193 bits/125 us  1.544Mbps
Signaling Info: carried in 1st bit of time slots 6-12
- leaves 7 bits for data
Frame synchronization: bit (framing bit) at start of ‘frame 1’
- toggles from 1,0 for consecutive frames
125 us
slot 23
slot 23
…
slot 1
slot 0
frame
bit
•slots 6,12: 1 signal bit, 7 data bits  56 kbps
•slots 7-11, 13-24: 8 data bits  64 kbps
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DS1 or T1 Link
64Kbps links digital links
0
1
..
23
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clock=8
KHz
….
193 bits
slots
1,0 23
….
1,0
synch bits
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E1 Link: (ITU-T)
• 30 voice channels at 64Kbps  1.920 Mbps
• two additional slots for signaling and control
32  (8/125us) = 2.048 Mbps
• Signaling info: carried in time slot 16
• Frame synchronization: time slot 0
- used for frame alignment
- allows receiver to interpret time slots in each frame on aligned
boundaries
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Higher Aggregate Link Rates: MUX several groups (DSxx, Ey)
• Higher order mux circuits: known as
- plesiochronous (nearly synchronous)
- asynchronous
• PDH: (plesiochronous digital hierarchy) results in higher-order
mux rates
• higher bit rate links require additional bits for framing & control
Link Type
E3 = 16  E1
T3 = 28  T1
64Kbps
channels
480
672
payload rate total rate including
control data
30.72Mbps
34.368Mbps
43.008Mbps
44.736 Mbps
Fractional T1, E1: Lower Bit Rates on T1, E1 systems
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T1 = 2464Kbps links + control
64Kbps links
0
1
..
23
0
1
..
23
T1 link 0
clock=8 KHz
T1 link 1
clock=8 KHz
T3 link
justification bit
0
1
..
23
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T1 link 27
T3 = 28T1 links + control
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Leased Line Interconnection
hub
hub
T3 lines
CSU/DSU router
router CSU/DSU
Public Carrier
Network
CSU/DSU
CSU/DSU
channel service unit (CSU):
•electrical barrier
•keep alive signal
•loopback test
data service unit (DSU) translate data format between entities
•T1 uses TDM DSX frames for Data
•LAN serial data frame format (e.g. ethernet)
•physical connector to LAN
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