The University of British Columbia
Electrical and Computer Engineering Department
EECE-256 Fall 2000 (Dr. Saif Zahir)
Solutions to Assignment No. 3
(Issued October 10, 2000)
Problem 1.
The following is a NAND-to-NAND gate network. Draw a block diagram
for a NOR-to-NOR gate network that realizes the same function, using as few gates as
possible.
_
A
_
C
_
A
_
B
F
_
C
_
D
A
_
C
Recall that a NOR gate can be used to implement all basic gates: AND, OR and
INVERTER. It can also be used to implement NAND as follows:
X
_
X
_____
_ _
X+Y
_ _ ____
X+Y = X.Y
X
=
Y
_
Y
Y
Therefore, we can replace all the NAND gates in given circuit with the NOR
representation shown above.
____
X.Y
_
A
_
C
_
A
_
B
F
_
C
D
A
_
C
When two inverters follow each other, they can cancel each other. So we can remove all
the cascaded inverters in the circuit above. In addition, since the variables and their
complements (i.e. both A and A') are readily available, we can remove the inverters at the
input and replace them with the complemented inputs as appropriate. Finally, the only
inverter left in the circuit is the one at the output. We can replace that with a NOR
implementation of an inverter (which is obtained by joining the two inputs of the inverter
to each other.
With the foregoing, the circuit above simplifies to:
2
A
C
A
B
F
C
_
D
_
A
C
Problem 2
Convert the following NOR-to-OR gate network to a NAND-to-NAND
gate network. Use as minimum gates as possible.
_
A
_
C
_
B
C
_D
A
_
D
F
Recall that a NAND gate can be used to implement all basic gates: AND, OR and
INVERTER. It can also be used to implement NOR as follows:
X
Y
_
X
_
Y
___
_ _
X.Y
_ _ _____
X.Y = X+Y
=
_____
X+Y
X
Y
3
The inverter at the output (in the circuit above) will be omitted when implementing an
OR gate with a NAND.
The given circuit now becomes:
_
A
_
C
_
B
C
F
D
_
A
_
D
Eliminating the cascaded INVERTERS and, taking advantage of the availability of
variables along with their inverted versions, we have the circuit below:
A
C
_B
C
_
D
F
A
D
4
Problem 3.
Use the Quine-McCluskey method to find the minimum equivalent forms
for the following Boolean expressions:
(i)
F(X,Y,Z) = m(2,3,4,5)
Write out the terms in binary form:
010
011
100
101
Create the Prime Implicant table
Column 1
010 
100 
Column 2
01_
10_
011 
101 
Draw the Prime Implicant chart
10_
01_
x
x
010
011
x
x
100
101
Essential prime implicants: 10_ and 01_ .

F = XY' + X'Y
(ii)
F(W,X,Y,Z) = m(0,1,4,5) and F(W,X,Y,Z) = d(12,13)
Write out the terms in binary form (including the “don’t cares”):
0000
0001
0100
0101
1100
1101
5
Create the Prime Implicant table (including the “don’t cares”).
Column 1
0000 
0001 
0100 
0101 
1100 
1101 
Column 2
000_ 
0_00 
Column 3
0_0_ *
_10_ *
0_01 
010_ 
_100 
_101 
110_ 
Draw the Prime Implicant chart (excluding the “don’t cares”)
0_0_
x
x
x
x
x
x
0100
0101
_10_
0000
0001
Essential prime implicants: 0_0_ .

Problem 4.
F = W'Y'
Given the function F(W,X,Y,Z) = m(1,5,7,8,9,15) + d(4,14), find the
minimum Sum-of-Products using Q & M method. Show your work including the charts.
Write out the terms in binary form (including the “don’t cares”):
0001
0101
0111
1000
1001
1111
0100
1110
6
Create the Prime Implicant table (including the “don’t cares”).
Column 1
0001 
1000 
0100 
Column 2
0_01 *
_001 *
100_ *
010_ *
0101 
1001 
01_1 *
0111 
1110 
_111 *
111_ *
1111 
Draw the Prime Implicant chart (excluding the “don’t cares”)
0_01
x
_001
x
x
x
100_
x
010_
x
01_1
x
x
x
_111
x
x
111_
x
0001
0101
0111
Essential prime implicants:
100_ .
Other prime implicants:
0_01, _111

1000
1001
1111
F = WX'Y' + W'Y'Z + XYZ
7
Problem 5. Design an AND-to-OR gate combinational network for the Boolean algebra
function:
F = W'X'Y'Z' + WX'Y'Z + WX'Y'Z' + W'XY'Z'
Use as few gates as possible.
Simplify the expression:
F = W'X'Y'Z' + WX'Y'Z + WX'Y'Z' + W'XY'Z'
= W'X'Y'Z' + WX'Y'Z' + WX'Y'Z + WX'Y'Z' + W'X'Y'Z' + W'XY'Z'
= X'Y'Z' (W' + W) + WX'Y'(Z + Z') + W'Y'Z'(X' + X )
= X'Y'Z' + WX'Y' + W'Y'Z'
Implement the logic circuit.
W
X
Y
Z
X'Y'Z'
WX'Y'
F
W'Y'Z'
8