Learning Activity 5
Testing complete RISC-V 32I CPU
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Requirements
• For this learning activity, you will write a RISC-V
assembly program to more thoroughly test your
RISC-V CPU design
• You will use a skeleton program that is commented
to indicate the specific functionality you are required
to implement
• The program calls functions, each of which tests a
subset of the complete RISC-V 32I instruction set
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Requirements
• The program loads each register with its register
number in a diverse fashion
– For example, x1 = 1, x2, = 2, and so forth
• Then, these values are stored in the first 32 RAM
locations, the registers are reset to zero, and then the
values are diversely loaded back into the registers
• If the CPU design you submit produces the correct
output for both the registers and RAM, you will be
awarded 100% for this learning activity
• If you CPU design does not produce the correct
output, you will be awarded 0% for this learning
activity
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Test Program Output
• At the end of the program,
registers x2 through x30
contain values 2 through 30
– Register x1 will contain a value that
represents the return address from
the last function call
– And x31 will contain the value
0x2000, the start of RAM
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Test Program Output
• Likewise, RAM[2] through RAM[30] contain values 2
through 30
– Again, RAM[1] will contain a function return address
– And RAM[31] will contain 0x2000
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Submission
• Note that no Verilog files are required for submission
• You must submit:
– The assembly program you wrote and used for testing
» Note that this is not the machine code file that you use for your
Verilog simulation
– Simulation-based verification (as a PDF file) that RISC-V CPU
design matches the program executing using RARS
• Note that comparison of results with an instruction
set simulator is the only acceptable verification
• Also, you must demonstrate that both RAM memory
and the CPU register results match
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