CMOS Static Logic Gates
■
ÒStaticÓ -- logic levels remain valid so long as power is supplied
■
NOR and NAND gates
VDD
M4
A
M3
B
+
M2 VOUT
_
M1 B
A
(a)
VDD
M3
A
M4
A
B
+
B
M2
M1
(b)
VOUT
_
CMOS NAND Gate
■
Qualitative description
Find transfer curve for case where VA = VB and both transition from 0 to 5 V
■
Transistors M1 and M2 are in series and have the same current; however, they do
not have the same gate-source bias
VDD
VM
M3
M4
ID
VM
VM
VGS1 = VM
M2
+
M1 VDS1
VGS2 = VM − VDS1
ID1 = ID2
−
VDS
(a)
(b)
MOSFETs in Series
■
Transistors M1 and M2 are Òin seriesÓ with the same gate voltage, for the case
where the inputs are tied together (A = B)
VOUT
M1
VA = VB
M2
ground
drain current is the same through each device ... what is the effective value of kP?
MOSFETs in Series (Cont.)
■
At VA = VB = VM, the cross section through M1 - M2 is:
,,
,,
VM
,,
,,
source
VM
gate
gate
M1
M2
n+
L1
L2
(a)
,,
,,
drain
VM
,,
source
VM
gate
gate
M1
M2
L1
L2
,,
drain
(b)
■
Transistor M1 is in triode and M2 is saturated. From the cross section, the drain
of M1/ source of M2 can be eliminated without affecting anything --> the two
MOSFETs can be merged into a composite transistor with L1 + L2 = 2 Ln
■
Solving for VM for the case where VA = VB (note that the two p-channel devices
are in parallel and have an effective width of W3 + W4 = 2 Wp
2k p
kp
V Tn + 2 ----- ( V DD + V Tp )
V Tn + ------------ ( V DD + V Tp )
kn ⁄ 2
kn
V M = ------------------------------------------------------------------ = --------------------------------------------------------------2k p
kp
1 + -----------1 + 2 ----kn ⁄ 2
kn
where kn = µnCox (Wn/Ln) and kp = µpCox (Wp/Lp)
We could optimize VM = VDD/2, but there is another switching condition to consider
CMOS Static NAND Gate
■
Second switching condition: VA = VDD and VB switches from 0 to VDD
VDD
VDD
M3
ID
M4
VGS1 = VDD
VM
VM
M2
+
VGS2 = VM − VDS1
ID1 = ID2
M1 VDS1
_
VDS
(a)
(b)
At VB = VM, the current through M1 and M2 is higher than when VA = VB since
the gate voltage on M1 is now VDD and its VDS1 must be smaller --> VGS2 is
larger. Effective kn is increased.
At VB = VM, only M4 is conducting current --> only half the current as for
previous switching condition. Effective kp is that of device M4
■
Result: VM is 0.3-0.5 V lower than for VA = VB switching condition, for typical
dimensions
NAND Gate Transfer Functions
■
SPICE is useful to solve for the transfer functions under the various switching
conditions (see Ex. 5.7). Note that the backgate effect means that the curves
when VA switches and when VB switches are not identical.
VOUT
(V)
Transfer Functions
5.0
4.0
B SWITCHES
A SWITCHES
A & B SWITCH
3.0
2.0
1.0
0.0
0.0
■
1.0
2.0
3.0
4.0
Results: setting kn = 2 kp results in VM approximately VDD/2.
5.0
VIN (V)
CMOS NAND Gate Transient Analysis
■
Worst-case situation for low-to-high transition: only one of the p-channel
transistors is switching (say M4):
kp
2
Ð I Dp = Ð I D4 = ----- ( V DD + V Tp )
2
■
■
For high-to-low transition, consider M1 and M2 in series with effective length at
2Ln (worst-case since current is lowest with VA = VB)
kn
2
2
I Dn = I D = I D2 = µ n C ox [ W n ⁄ 2 ( 2L n ) ] ( V DD Ð V Tn ) = ----- ( V DD Ð V Tn )
1
4
For equal propagation delays, we require IDn = -IDp
kn
kp
----- = ----- --> kn = 2kp
4
2
The factor of 2 mobility difference between the p and n channels indicates that
(W/L)n = (W/L)p (2 input NAND gate)
■
For an M-input NAND gate, we find that
(W/L)n = (M/2) (W/L)p
Note: NOR gates suffer from a factor of 2M between the n- and p-channel ratios
which makes them unattractive for large fan-in gates
CMOS Dynamic Logic
■
Static NOR gate
VDD
A
M4
B
M3
Q
A
M1
B
M2
CL
Idea: n-channel and p-channel devices separately perform the same logic function.
replace p-channels with a resistor -->
Q = A+B
replace n-channels with a resistor -->
Q = AB
... two functions are identical by DeMorganÕs Theorem
■
Let n-channels perform the logic and get rid of the pull-up devices
(or vice versa)
n-Channel CMOS Dynamic Logic
clock signal φ(t) charges up load capacitance through MP (P = precharge) when
it transitions from high to low; ME (E = evaluate) is cutoff and prevents any
discharge path of CL through logic function transistors.
■
clock signal goes high --> MP is cutoff, ME conducts --> CL discharges if one of
the logic transistors has a high input.
■
VDD
φ
φ
A
B
MP
C
M
CL
+
VOUT
VDD
−
evaluate
evaluate
precharge
0
Logic
Function
φ
ME
(a)
■
t
(b)
Payoffs:
1. large fan-in NOR gates without huge p-channel load devices (also, avoids
backgate effect on loads)
2. tends to be fast due to smaller load capacitances
■
Drawback:
1. clock is essential to refresh logic level stored on CL, which complicates the
design
n-Channel Dynamic Logic Propagation Delays
■
Consider ÒtPLHÓ to be the time required to pre-charge the output node
Precharge Circuit (tPLH)
VDD
φ=0
MP
VOUT (t = 0) = 0 V
CL
A
■
B
M
φ=0
ME (cutoff)
Charging current
kp
2
Ð I Dp = ----- ( V DD + V Tp )
2
n-Channel Dynamic Logic Propagation Delays
■
Consider ÒtPHLÓ to be the worst-case time to evaluate the logical function after
clock goes high.
Evaluate Circuit (tPHL)
(only one input high)
φ=5V
VDD
MP (cutoff)
VOUT (t = 0) = 0 V
CL
5V
0V
φ=5V
■
0V
ME
Discharging current: assume (W/L)E = (W/L)A = ... (W/L)M and note that the
transistors are in series -->effective value is kn / 2
kn
2
I D = µ n C ox  ----- ( V DD Ð V Tn )
 4
n
Boolean Functions in Dynamic Logic
■
Examples:
VDD
φ
VDD
φ
MP
ME
Q
A
A
B
C
D
B
C
Q
φ
φ
ME
(a)
■
MP
(b)
(a) n-channel dynamic logic
Q = ( A + B )C
■
(b) p-channel dynamic logic
The output is Òpre-dischargedÓ to zero by MP and is only charged if there is a
path through the logic transistors when the clock goes low and ME conducts.
Q = AB + C + D
CMOS Transmission Gates
■
Need: ÒgateÓ signals by having a series switch that can be shorted or opencircuited.
C
C
IN
OUT
OUT
IN
C
C
(a)
■
(b)
Why n-channel and p-channel in parallel? Only one device (say, n-channel):
canÕt pass an input voltage > VDD - VTn, since device will enter the cutoff region
.
G
G
5V
S
D
5V
B
0V
(a) charge-up
5 V − VTn
0V
D
S
0V
B
5V
(b) discharge
0 V − VTp
Pass Transistor Logic
■
Advantages: reduced transistor count and higher speed compared with static
CMOS
■
Disadvantage: reduced noise margins
B
B
A
B
B
B
OUT
OUT
A
B
(a)
(b)
Switching
Network
(c)