Innovus P&R
INTRODUCTION TO
INNOVUS
PLACE & ROUTE
(version 1.2021)
Sistemas Eletrónicos Integrados
(Period 1)
João Vaz
Instituto Superior Técnico
2021/2022
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João Vaz
Innovus P&R
SEI 2021/2022
João Vaz
• Introduction
Cadence Innovus Implementation System is a family of software
programs that perform all the flow steps to transform a digital circuit
RTL description into a GDSII layout representation ready for fabrication
submission.
This tutorial explains the place and route (P&R) phase.
• Place and Route typical flow
Innovus P&R
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• Innovus first-time configuration
It is assumed that a Verilog netlist with standard cells module was already
synthesized. In this tutorial a four bits counter (counter4bit_gates.v) will be used.
First of all, for organizing reasons, it is better to create a directory where your
designs will be kept. In this tutorial that directory name will be DIGITAL
Inside DIGITAL directory create the directory P_and_R where all tasks of digital flow
place and route will be made.
Inside DIGITAL/P_and_R run the command
$ /opt/ic_tools/pdk/faraday/cdsenv/innovus/create_lef_libs
and create also the directory COUNTER4BIT dedicated for this tutorial example.
Change to DIGITAL/P_and_R/COUNTER4BIT directory.
Finally, counter4bit_pr.tar should be copied to this directory. To untar use the
command
$ tar –xvf counter4bit_pr.tar
Three files (captable.cap, counter4bit.view, counter4bit.globals) will be obtained.
Innovus P&R
• Running the software
The script that must be run before using the software is:
$ source /opt/ic_tools/init/init-innovus20-11-hf000
The software is started with the
command
$ innovus
(Note: Do not use “innovus &” because
the terminal window needs to be used
by the software)
• Innovus interface
A terminal and a graphical interface
appear. Both can be used to enter
commands and see results; however
terminal commands list is more
extensive.
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Innovus P&R
• Reading files
Using menu “file/import design”
by selecting “Load” and
reading conter4bit.globals, the form is
filled automatically
Advise: to avoid filling all the info next time you make the same
design import, use “save” and ”load” to fill all forms automatically.
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Initialization input files
Verilog files have a netlist of standard/macro
cells (sometimes called gatelist). These files
are generated by synthesis phase.
LEF files have the abstract layout views of
standard/macro cells showing dimensions,
PG and IO pins. Additionally, they have also
electrical properties and design rules for
vias and metal layers. They can also include
information to solve antenna errors.
If IO configuration file is already available, it can be loaded at this stage.
Power and ground (PG) nets should be defined at this stage (for example dvdd and
dgnd). They will be the global PG nets. Their names can be equal or not to standard
cells PG pins.
If available, the MMMC configuration file can also be loaded at this stage.
Innovus P&R
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Terminal commands:
If counter4bit.globals was previously saved, use the following commands to
initiate the design:
innovus > source counter4bit.globals
innovus > init_design
Please note that the gate netlist is loaded in this step.
Note: logs generated after this phase should be checked.
Also, the command
innovus > check_timing –verbose
can be used to check if there are timing problems with the constraints and
design.
Finally, the command
innovus > checkDesign –all
can be used to check if there are any errors.
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Innovus P&R
• Floorplan (FP)
Using menu “floorplan”
/ Specify Floorplan…
use Core
to IO =
3.6um (not
2.4um)
The standard cells have fixed 3.2um height, and 0.4um multiples width. Track routes (middle line of a path) are
spaced by 0.4um in both vertical and horizontal directions. It is better to check the initial layout size and chose
the core size of appropriate value maintaining a core utilization around 60 to 70%. The layout grid is 0.01um.
The core height should be a 3.2um multiple and the core width 0.4um multiple. Core to IO margins should be
0.4um multiples. After creating the FP all the gatelist pins are concentrated at the layout origin by default.
Innovus P&R
• Power
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Using menu “power/connect global nets”
The “Pin Names” are
the standard cells PG
pins, in this case VCC
and GND. In “scope”
use “apply all”.
The “Global Nets” are
the ones defined in
file/import, which are
dgnd and dvdd.
If the gatelist has 1’b1
or 1’b0, tie high and
tie low connections to
global nets should be
added.
The connection list is
made by adding each
node type at a time. In
the figure dgnd to
GND connection was
made first.
Innovus P&R
• PG rings
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Using menu “power/power planning/add rings”
There are two ways to add the PG rings:
i) one at each time: In “Net(s)” only one node is written, the metal type and width for each
side is chosen, and the offset to core. Spacing is not used.
ii) all at the same time: The same as i) but with spacing between rings.
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Additional remarks:
The metals routing has, by default, some rules that are related with the vertical
or horizontal direction of the paths. For example
M1, M3, M5, … prefer to use horizontal direction
M2, M4, M6,… prefer to use vertical direction
If on the layers control window “tracks” are set visible, a grid of track lines will
be visible. The color of these line correspond to the metal colors. The “Pref
tracks” are the preferred and the “NPref tracks” are the non preferred tracks.
This is why, by default, “add rings” menu uses horizontal M1 and vertical M2.
For this simple example M1 and M2 rings will be used.
Innovus P&R
• Special route
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Using menu “route/special route”
The special route creates M1 horizontal stripes and connect them to PG rings.
These stripes that will have alternatively dgnd and dvdd to bias the STD cells.
Finally, “verifyGeometry” terminal command should be run to check for
possible DRC errors.
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• Pin’s editor
Using menu “edit/pin editor”
Usually, the previous pins placement is not
the one that the designer wants.
This task can be made after FP, but it will
be explained now when FP and PG rings
are already created.
Using the pin editor form it is possible to:
1) Place pins in a certain IO boundary side
2) Place pins in a certain metal layer
3) Place pins in a certain position
Each modification will be visible in the
layout after pressing apply. Groups of pins can be defined which is useful to
create buses from individual pins.
test
different pin
Finally, it is possible to “assign a fixed status” for selected pins. This way
locations and press
following design phases like place or route won’t change pin’s locations.
“Apply” to check
It is important to place pins on tracks and spaced apart of 0.4um multiples.
result
Use odd metals for horizontal pins, and even metals for vertical pins.
In the end the pins arrangement can be saved in a file for future loading using
the menu “file/save/IO file”.
Innovus P&R
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Now the pins are placed on different sides, with a certain order and location.
Right side pins
Left side pins
Bottom side pins
Innovus P&R
• Add stripes (optional)
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Using menu “power/power planning/add stripes”
In large area designs standard cells bias can be improved by placing vertical stripes
connecting PR rings to inner points of horizontal PG rows. This way bias IR drop for cells far
away from rings is minimized.
Usually an upper metal (M7 in this case) is chosen because it has lower resistance than M1-M6.
By the same reason PG rings can be made with higher metals like M6-M8. When using M8, vias
V78 are required but, because of its size, a larger space between core to IO boundary is needed
(the 2.4um of this example is not enough).
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• Well taps and Endcaps (during FP)
When available well tap cells can be placed in the design to improve n/p wells
bias.
When available endcaps are cells that can be placed in the design for providing
an AC shunt capacitor (MOS type) between P and G. Usually they are placed in
the PG rows extremes.
The pdk in use does not provide this kind of cells.
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Innovus P&R
• MMMC configuration
Using menu “timing/configure MMMC”
First time configuration can be done with GUI interface. In this technology case only two delay
corners, best case – BC (ff lib and lower RC parasitics), and worth case – WC (ss lib and higher
RC parasitics) can be created.
Corner
conditions were loaded during
design import from file
counter4bit.view
Configuration can be saved. In the next design initialization, during import design phase, the
saved file can be in included on the bottom of the form.
Note: RC corners should only be created if captable.cap file is available. The cap table file can be
generated by encounter if an .ict tech file is available from the PDK.
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Inputs for timing analysis
MMMC filling for BcWc case, where two corners (ff and ss) are provided in pdk.
Library sets: Timing libraries for BC (ff) and WC (ss) used during synthesis. These
libraries take into account standard cells PTV information.
RC corners: If cap table is only available for typical corner (tt), two RC corners can
be build based on tt. One for +10% R and C dispersion and 125º, other for -10% R
and C dispersion and -40º. RC corners are related with interconnect parasitics.
Delay corners: Build for WC and BC using correspondent timing libraries and RC
corner.
Constraint modes: SDC file from synthesis must be selected.
Views configuration for timing analysis
Analysis views (including setup and hold views): Build for WC and BC using
correspondent delay and RC corner.
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Menu final commands commands:
Up to a certain FP stage, the design floorplan can be saved and loaded using the
GUI file menu. The saved FP contains also the IO pins location.
Equivalent terminal command:
To save the design FP use the following command
innovus > saveFPlan counter4bit_PG_rings.fp
To load a design FP use the following command
innovus > loadFPlan counter4bit_PG_rings.fp
Before start placing it is advisable to make if CMOS is 130nm
innovus > setDesignMode -process 130
Like this several default options for the following steps are automatically
chosen.
After completing floorplan, the pre-place stage is reached
Innovus P&R
• Timing analysis
Using menu “timing/Report timing”
Report timing can be performed in the preplace design phase.
Setup type should be performed. Hold type is
only available in Pre-CTS design phase. Output
appears on terminal window.
Worth negative slack (WNS) must be positive.
Total negative slack (TNS) also.
At this design phase (Pre-Place) the gatelist
can be almost equal to synthesis gatelist, so
usually there are no timing problems, except if
the were inherited from synthesis.
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Innovus P&R
• Place
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Using menu “place/place standard cell”
The standard cell are placed in
the core, and by default, an
initial routing draft is made (no
free from drc errors). If the pins
were still in the origin, they are
placed around the die borders
in the most convenient way to
minimize routing.
Pre-Place optimization option is selected by default which it is advisable. The other
options can be seen in “Mode” menu, selecting “Place”.
Innovus P&R
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Equivalent terminal command:
To place the design with default options, use the following super command
innovus > placeDesign
Please note that terminal commands cannot exactly have the same options of
menu command. The log file .cmd shows what the menu commands really do.
If necessary, at any stage, the complete design can be erased for starting a new
one by using
innovus > freeDesign
After placement, the pre-CTS stage is reached.
Each command given by the graphic interface or by command line is stored in file innovus.cmd# :
innovus.cmd - commands given in the first execution of innovus
innovus.cmd1 - commands given in the second execution of innovus
…
innovus.cmd12 - commands given in the 13th execution of innovus
… (note that these files can be edited)
While executing innovus, a previous set of commands can be executed by:
innovus> source innovus.cmd5
//this will repeat execution of all commands in innovus.cmd5 file
Innovus P&R
• Timing analysis
In pre-CTS an initial not precise routing is
made, so timing analysis should be
repeated.
Setup and Hold should be performed, to
check negative WNS.
Output appears on terminal window.
WNS must be positive and design rules
violation (DRV) absent. Total negative
slack (TNS) also.
• Optimization
Using menu “ECO / Optimize Design”
If negative Setup WNS or DRV were found,
optimization can be performed to solve
them.
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Innovus P&R
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• CTS (clock tree synthesis)
The Clock Tree Synthesis phase includes buffers/inverters in the clock tree to
cope with fanout and skew. During initial design import phase innovus analyses
and automatically select from .lib standard cells the buffers, inverters and delay
cells that are suitable to use in the clock tree. This choice can be override by
the user.
To perform CTS use the terminal command
innovus > ccopt_design
After CTS, results can be viewed with
innovus > report_ccopt_clock_trees
innovus > report_ccopt_clock_structure
On “Clock/CCOpt Clock Tree Debugger” menu a GUI interface is available.
After CTS, the pos-CTS stage is reached.
Innovus P&R
• Timing analysis
In pos-CTS timing analysis should be
repeated.
Setup and Hold should be performed, to
check negative WNS and DRV.
• Optimization
Using menu “ECO / Optimize Design”
If negative Setup or Hold WNS values and
DRV were found, optimization can be
performed to solve them.
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Innovus P&R
• Nano route
Using menu “route/nanoroute/route”
The NanoRoute consists of
global Route and then on
detail Route. The previous Post-CTS route is optimized.
Command like “verify_drc” and “verify_connectivity” should be run to see if there are
any errors.
It is possible to chose which metal levels are used in option “Mode”.
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Innovus P&R
• Timing analysis
In post-Route timing analysis should be
repeated.
Setup and Hold should be performed, to
check negative WNS.
• Optimization
If negative Setup or Hold WNS values and
DRV were found, optimization can be
performed to solve them.
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Innovus P&R
Equivalent terminal command:
To route the design with default options, use the following super command
Encounter > routeDesign
After finishing nanoroute the design stage is post-route
Timing analysis should be performed, and optimization can be repeated.
But for timing analysis to work the following command should be given:
innovus > setAnalysisMode -analysisType onChipVariation
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Innovus P&R
• Filler cells
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Using menu “place/physical cell/add filler”
Filler cells will fill the core empty space and additionally help biasing n-well and p-well on empty space.
Run again “verifyGeometry” and “verifyConnectivity”. The layout is now ready for fabrication.
Please note that one important aspect is neglected during this simple tutorial, the time optimization and
analysis. Additionally, all optimizations were made using default options.
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• Sign-off
At this stage the design is almost ready for fabrication.
Several analysis should be made, like, timing analysis, final DRC, logical
equivalence (LEC), etc.
innovus > checkDesign –all
can be used to check if there are any errors.
A final gate netlist can be generated with
innovus > saveNetlist counter4bit_pr.v
A LEF view of the counter can be automatically generated with
innovus > write_lef_abstract conter4bit.lef