IET Circuits, Devices & Systems
Research Article
Low-voltage fully differential difference
transconductance amplifier
ISSN 1751-858X
Received on 7th February 2017
Revised 11th May 2017
Accepted on 23rd May 2017
E-First on 3rd November 2017
doi: 10.1049/iet-cds.2017.0057
www.ietdl.org
Fabian Khateb1,2 , Montree Kumngern3, Tomasz Kulej4, Vilém Kledrowetz1
1Department
of Microelectronics, Brno University of Technology, Technická 10, Brno, Czech Republic
of Biomedical Engineering, Czech Technical University, Prague, nám. Sítná 3105, Kladno, Czech Republic
3Department of Telecommunications Engineering, Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang, Bangkok 10520,
Thailand
4Department of Electrical Engineering, Technical University of Częstochowa, 42-201 Częstochowa, Poland
E-mail: khateb@feec.vutbr.cz
2Faculty
Abstract: A new complementary metal–oxide–semiconductor (CMOS) structure for fully differential difference transconductance
amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the
circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages.
The QFG multiple-input metal–oxide–semiconductor transistor is used to reduce the count of the differential pairs that needed to
realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 µW. The FDDTA
was designed in Cadence platform using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company
(TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to
confirm the attractive features of the proposed CMOS structure of the FDDTA.
1
Introduction
Active elements such as differential difference amplifiers (DDAs)
and differential difference operational floating amplifier (DDOFA)
are useful blocks in analogue signal processing [1–4]. Thanks to
their two differential input ports they have the capability of
performing arithmetic operations (voltage summation and
subtraction). The advantage of using the DDA and the DDOFA is
that the number of active and passive elements used for their
applications can be reduced which is suitable for special voltagemode circuits. The symbol of the DDA is shown in Fig. 1a and the
output voltage is given by
V out = A (V 1 − V 2) − (V 3 − V 4)
(1)
where A is the open-loop gain of DDA. If this open-loop gain is
very large and with this definition, the property the DDA with
negative feedback can be written as: V1–V2 = V3–V4.
The symbol of the DDOFA is shown in Fig. 1b. The structure of
this device is based on cascading connection of differential
difference transconductor and transresistance amplifier [3, 4].
Therefore, it has two differential input terminals and two balanced
output currents. The ideal characteristic can be given as
Io + = − Io − = G (V 1 − V 2) − (V 3 − V 4)
(2)
where G is the open-loop transconductance gain of the DDOFA
and if G is very large the following expression can be obtained:
V1–V2 = V3–V4.
Although the DDA and the DDOFA have found many
applications their complementary metal–oxide–semiconductor
(CMOS) structures are not suitable for low-voltage operation (≤1
V). Nowadays, low-voltage low-power operation capabilities are
demanded mainly for portable and biomedical devices [5, 6]. In
CMOS technology, due to the high value of the threshold voltage,
reducing the voltage supply significantly limits the headroom of
circuit operation. Therefore, innovative design techniques such as
bulk-driven, floating-gate, quasi-floating-gate and their
combination have been adopted to overcome the high value of the
threshold voltage, to increase the input common mode range and to
maintain other circuit's performance acceptable [5–34].
Recently, a new active element FDDTA that use the same
concept of DDOFA was presented [31]. The floating-gate
technique was used to provide a low-voltage operation and a
multiple-input terminal hence the number of the differential pairs is
reduced. The FDDTA has two differential difference input
terminals (arithmetic operation capability of voltage signals) and
true balanced output currents are provided [31].
The circuit symbol of the FDDTA is shown in Fig. 2. It has six
input voltage terminals (V1–V6) and two output current terminals
(Io+, Io−). The ideal characteristic of FDDTA can be given by
Fig. 1 Circuit symbol of
(a) DDA and (b) DDOFA
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
73
Io + = − Io − =
1
(V − V 2 + V 3) − (V 4 − V 5 + V 6)
Rt 1
(3)
where Rt is the external resistor connected between the Z+ and Z−
terminals and is used to provide the value of the transconductance
(Gt = 1/Rt).
However, since the CMOS structure of the FDDTA presented in
[31] is based on the floating-gate technique it suffers from the
increased silicon area, initial charge trapped in the floating gates
and less value of the equivalent transconductance in comparison to
the conventional gate transconductance, resulting in gainbandwidth product degradation. It is interesting enough that these
limitations and drawbacks could be eliminated by using the
alternative QFG technique. Another limitation of the CMOS
structure in [31] is the class A output stages that limit the driving
capability of the circuit. The circuit in [31] was designed to work
with ±0.4 V voltage supply. Therefore, in this paper a new FDDTA
CMOS structure based on the quasi-floating-gate (QFG) technique
is presented. The circuit has class AB output stages and simple
CMOS topology with voltage supply of 0.6 V. To demonstrate the
features and the functionality of the proposed FDDTA two example
applications: a three-stage quadrature oscillator and fifth-order
elliptic low-pass filter are presented.
The paper is organised as follows: the proposed CMOS
structure of the QFG-FDDTA is presented in Section 2.
Application examples using FDDTA as active elements is
presented in Section 3. The simulation results are shown in Section
4. At the end of the paper, the conclusion is addressed in Section 5.
2
Proposed FDDTA CMOS structure
The CMOS structure of the proposed FDDTA is presented in
Fig. 3. It consists of two differential input stages (M1, M2 and M11,
M12) based on the QFG technique. The gates of these transistors
are biased to VDD through high-resistance device created by diodeconnected transistor in cutoff (Mb1, Mb2 and Mb11, Mb12),
respectively, and are further connected to the input capacitors (C1–
C8) to create multiple-input MOS transistors and hence the number
of the differential pairs is reduced and the circuit topology is
simple compared to the conventional gate-driven design.
Transistors (MB and M4, M5, M6, M8, M14, M15, M16, M18) act
as a multiple output current mirror applying the constant current
source IB to each branch of the circuit. However, to achieve a class
AB output stage, that allows high current-drive capability and
simultaneously very low quiescent power consumption, the QFG
class AB current mirror is used [24–26]. The gates of the
transistors (M6, M8 and M16, M18) are connected to VB through the
diode-connected transistor in cutoff (M10 and M20), respectively,
under static condition the capacitors (C9 and C10) have no
influence so the voltage at the gates of the transistors (M6, M8 and
M16, M18) is VB since there is no current flowing across (M10 and
M20) and no voltage drop across them [24–26]. However, under
dynamic conditions, capacitor (C9 and C10) acts as a floating
battery, transferring AC signal variations from the gate of (M7, M9
and M17, M19) to (M6, M8 and M16, M18), respectively.
Transistors M3 and M13 act as tail current sources for the first
and second differential input stages, respectively. Transistors (M6,
M7 and M16, M17) create the second stage for the two differential
input stages, respectively. Due to the unity gain connection
between the output of the second stage and the input terminal of
the differential input the voltage transfers (between the input
voltages and Z) is ensured. Transistors (M8, M9 and M18, M19)
create the output stage for the FDDTA and they provide a current
copy of the Z terminal to Io. Finally, the compensation networks
(RC1, CC1) and (RC2, CC2) insure the stability of the circuit.
Note that the differential input stages and the tail currents (M1,
M2 and M3) (M11, M12 and M13) construct a flipped voltage
follower [12, 32] allowing reducing the voltage supply
requirement. Hence the minimum power supply voltage VDD.min is
given by
V DD . min = V GS, M3, M13 + V DS, M5, M15
(4)
Equation (4) shows the capability of the proposed QFG-FDDTA
structure for operation under lower supply voltage.
A straightforward analysis of a small-signal equivalent circuit
brings the following expressions for the voltage transfer ratios:
gmeff , M2rout1(gm, M6 + gm, M7)rout2
gmeff , M2
VZ +
≃ 1 (5)
=
≃
V 1, 2, 3 1 + gmeff , M1rout1(gm, M6 + gm, M7)rout2 gmeff , M1
where
rout1 =
1
1
and rout2 =
go, M1 + go, M4
go, M6 + go, M7
gmeff , M12rout11(gm, M16 + gm, M17)rout12
VZ −
=
V 4, 5, 6 1 + gmeff , M11rout11(gm, M16 + gm, M17)rout12
gmeff , M12
≃
≃1
gmeff , M11
(6)
where
Fig. 2 Proposed circuit symbol of FDDTA
Fig. 3 Proposed CMOS structure of the FDDTA
74
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
Fig. 4 FDDTA-based three-stage quadrature oscillator
rout11 =
1
1
and rout12 =
go, M11 + go, M14
go, M16 + go, M17
2
vnt
=2
The current transfer ratios
vn2 1/ f = 2
2
gm4, 5
8kT 2Ci + Cgs1, 2
⋅ 1+
3gm1, 2
Ci
gm1, 2
2
KFn
KF p gm4, 5
1 2Ci + Cgs1, 2
⋅
+
Ci
(WL)1, 2 (WL)4, 5 gm1, 2
f COX
(15)
2
(16)
gm, M8 + gm, M9
Io +
=
≃1
IZ +
gm, M6 + gm, M7
(7)
gm, M18 + gm, M19
Io −
=
≃1
IZ −
gm, M16 + gm, M17
(8)
where Ci = C1–8, KFn, KFp are the flicker noise constants for n- and
p-channel transistors, respectively, and the other symbols have
their usual meaning.
As we can conclude from (13)–(16) the output noise depends on
the noise contributed by the input stages of the FDDTA and the
resistance Rt.
1
gmeff , M1rout1(gm, M6 + gm, M7)
(9)
3 Application examples using FDDTA as active
elements
1
gmeff , M11rout11(gm, M16 + gm, M17)
(10)
The resistance of the Z+ and Z− is
RZ + ≃
RZ − ≃
Based on (9) and (10), the Rz+ and Rz− have low resistance values
as expected for a voltage follower.
Finally, the resistance of the Io+ and Io− terminals can be
expressed as
RIo + ≃
1
go, M8 + go, M9
(11)
RIo − ≃
1
go, M18 + go, M19
(12)
Based on (11) and (12), the RIo + and RIo − have high resistance
values as expected for a current output.
In (5)–(12), the gm and gmeff denote the gate and the effective
QFG transconductance of metal–oxide–semiconductor transistor,
respectively, and go is the transistor output conductance.
Neglecting the second order effects, within the circuit normal
bandwidth of operation the output noise current (spectral density)
of the FDDTA could be approximated as
2
iod
≅ (Gt | | gout1)2vn2 + 4kTGt
(13)
where Gt = 1/Rt, gout1 = 1/rout1 and
2
vn2 = vnt
+ vn2 1/ f
(14)
2
where vnt
and vn2 1/ f are the thermal and flicker noise components
given by
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
In this section, two application examples based on the proposed
QFG-FDDTA are presented. The first example is the FDDTAbased three-stage quadrature oscillator and the second one is the
FDDTA-based fifth-order elliptic low-pass filter.
3.1 FDDTA-based three-stage quadrature oscillator
For the full chip of continuous-time filter implementation with
automatic tuning frequency, oscillator is an important circuit that
can be used in phase-locked loop (PLL) [35]. A voltage-controlled
oscillator (VCO) is needed to serve this application where the
oscillating frequency of VCO can be controlled by varying the
amplitude of an input voltage signal. Although there are a lot of
oscillators can be used to work as VCO, but the three-stage
oscillator is normally used to realise VCO, because its structure is
simple and it is easy to control the oscillating condition. Compared
with a two-stage oscillator (second-order oscillator) three-stage
oscillator is higher-quality circuit that offers lower phase noise [36]
and better temperature stability [37]. Therefore, continuous-time
filters with automatic tuning frequency are normally used threestage oscillator (or ring oscillator) to apply in PLL [35, 38].
The FDDTA-based three-stage quadrature sinusoidal oscillator
is proposed as first example application as shown in Fig. 4. The
structure consists of two lossy and one lossless integrator [39]. The
system can generate sinusoidal signals same as the conventional
three-stage ring oscillator except the relationship of input and
output signals of the last stage (Vout1 and Vout2) which are
sinusoidal signals with phase difference 90°. Using the
characteristic of lossless integrator that has phase difference 90°
between input and output, thus it can be confirmed that Vout1 and
Vout2 of Fig. 4 are quadrature sinusoidal signals. A single signal
can be obtained using Vout1 or Vout2.
The characteristic equation can be given as
75
Fig. 5 Fifth-order elliptic low-pass filter
(a) LC-ladder prototype, (b) FDDTA-based filter
s3C1C2C3Rt1Rt2Rt3 + s2 C1C3Rt1Rt3 + C2C3Rt2Rt3 + sC3Rt3 + 1
(17)
=0
The condition of oscillation (CO) and frequency of oscillation (FO)
can be given as [39]
CO:
C1C3Rt1Rt3 + C2C3Rt2Rt3 − C1C2Rt1Rt2 = 0
FO:
ωo =
1
C1C2Rt1Rt2
(18)
(19)
Letting Rt1 = Rt2 = Rt and C1 = C2 = C3 = C, (18) and (19) are,
respectively, simplified as
Rt3 = 0.5Rt
1
ωo =
CRt
(20)
3.2 FDDTA-based fifth-order elliptic low-pass filter
Usually, fifth-order elliptic filter can be realised from signal-flow
graph corresponding to a standard fifth-order low-pass LC-ladder
circuit [40]. Using this synthesis process, the fully differential fifthorder elliptic low-pass filter using FDDTA as active element is
shown in Fig. 5. Fig. 5a shows the prototype of single-ended fifthorder elliptic low-pass ladder filter that is the solution to achieve
Fig. 5b. The proposed filter in Fig. 5b is modified from singleended fifth-order elliptic OTA-C filter in [41]. Thanks to using
multiple-input transconductor in filter design the number of
components can be reduced [42]. Hence, the proposed fully
differential filter consists of five identical FDDTAs and five
capacitors. Rs = Rt1 and RL = Rt5 is used for Fig. 5. The cutoff
frequency of the FDDTA-based filter is proportional to 1/RtC and
is adjusted by changing the Rt value. Letting Rt1 = Rt2 = Rt3 = Rt4 =
Rt5 = Rt, the transfer function of fifth-order elliptic low-pass filter
in Fig. 5 is expressed by
H(s) =
(21)
From (20) and (21), the CO can be controlled by Rt3 and FO can be
controlled Rt.
V out s
As4 + Bs2 + C
=
5
4
V in s
Ds + Es + Fs3 + Gs2 + Hs + K
(22)
where (see equation below)
4
Simulation results
The circuits were designed and simulated using 0.18 µm CMOS
process from TSMC with single supply of 0.6 V. The optimal
A = Rt7CL2 1CL2 2C2C4
B = Rt5 CL2 1CL2C2 + CL2 2CL1C4
C = Rt3CL1CL2
D = Rt8CL2 1CL2 2 C4 + C5 C1C2 + C1C3 + C2C4
E = Rt7CL2 1CL2 2 2C1C2 + 3C2C4 + C3C2 + C3C4 + C5C2 + C5C3 + C5C4
F = Rt6CL2 2CL1 C1C4 + C1C5 + C3C4 + C5C3 + C5C4 + Rt6CL2 1CL2 2 C2 + C3 + C4
+Rt6CL2 1CL2 C5C1 + C5C2 + C1C2 + C1C3 + C1C4 + C2C3 + C2C4
G = Rt5CL2 1CL2 C2 + C3 + C5 + Rt5CL2 1CL2 C1 + 2C2 + C3 + Rt5CL2 2CL1 C1 + C3 + C5 + 2C4
H = Rt4CL2 2 C4 + C5 + Rt4CL1 CL2 2 + CL2C5 + CL2C1 + Rt4CL2 1CL2
K = 2Rt3CL1CL2
76
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
Table 1
Component values and transistor aspect ratios for the FDDTA in Fig. 3
W/L, µm/µm
M1, M2, M11, M12,
64/3
M3, M13, M4, M5, M14, M15, MB
40/3
M6, M8, M16, M18
80/3
Mb1, Mb2, Mb11, Mb12, M10, M20
15/5
C1–C8 = 0.5 pF
C9, C10, CC1, CC2 = 3 pF
RC1, RC2 = 7.8 kΩ
VDD = 0.6 V
VCM = VDD/2 = 0.3 V
Ibias = 5 µA
Table 2 Performance comparison of proposed FDDTA with other low-voltage active building blocks
Parameters
Unit This work
Lehmann and Grech et al. [44] Chatterjee et al.
Ferreira et al. Rezaei and Azhari
(simulation)
Cassia [43]
(simulation) [35] (experimental) [45] (simulation)
[46]
(experimental)
(experimental)
device
MOS technique
CMOS
technology
power supply
power
consumption
unity-gain
bandwidth
FDDTA
QFG
µm
0.18
Op-amp
bulk-driven,
subthreshold
0.5
OTA
bulk-driven
OTA
bulk-driven
OTA
bulk-driven
0.18
OTA
bulk-driven,
subthreshold
0.35
0.35
V
µW
0.6
40
1.0
40
1.0
5
0.5
110
0.6
0.55
0.5
60
MHz
1.4
2
0.371
2.2
0.017
17.8
0.18
Fig. 6 Frequency responses of voltage gains VZ+/V1, and VZ−/V5
transistor aspect ratios and the bias components are given in
Table 1. The static power consumption of the proposed FDDTA is
40 µW.
Table 2 shows the performance comparison of the proposed
FDDTA with other low-voltage active building blocks: operational
amplifier (op-amp) and operational transconductance amplifier
(OTA). It obviously shows the low voltage and low power
operation capability of the FDDTA. Moreover, due to the
arithmetic operation capability of FDDTA the number of active and
passive elements of the FDDTA based applications is minimised,
consequently, the total power consumption is reduced.
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
4.1 Simulation results of the proposed FDDTA
Selected simulation results of the proposed QFG-FDDTA are
shown in Figs. 6 and 7.
The frequency responses of the voltage gains VZ+/V1, and VZ
−/V5 (where Vin = V1 = V5 and V2 = V3 = V4 = V6 = VCM) are shown
in Fig. 6. The low-frequency voltage gain is equal to 1 and the −3
dB bandwidths is 1.4 MHz.
The low-frequency current gain Io+,−/IZ+,− (where V1–V6 = VCM)
is also equal to 1 and the −3 dB bandwidth is 15 MHz. The
resistance of Io+,− terminals is 0.985 MΩ.
The current transient response of Z + , Z−, Io+, Io− terminals
with input voltage source of 100 mV and 10 kHz connected to V1
77
Fig. 7 Transient response of the IZ+, IZ−, Io+, Io−
Fig. 8 Growing oscillations of the quadrature oscillator output voltages
and V5 (where V2 = V3 = V4 = V6 = VCM and Rt = 28 kΩ) are shown
in Fig. 7.
4.2 Simulation results of the FDDTA-based three-stage
quadrature oscillator
The simulation results of the proposed three stage quadrature
oscillator in Fig. 4 are shown in Figs. 8–10.
As an example design, C1 = C2 = C3 = 0.6 nF, Rt1 = Rt2 = 28 kΩ
and Rt3 = 10 kΩ were given. The growing oscillations of the
quadrature oscillator output voltages are shown in Fig. 8 whereas
the steady-state waveforms are shown in Fig. 9. The oscillation
frequency is 19.3 kHz and the total harmonic distortion (THD) is
0.64% for Vout1 and 1.3% for Vout2. The spectra of the oscillator
output voltages are shown in Fig. 10.
28 kΩ, C1 = 74 pF, C2 = 23 pF, C3 = 133 pF, C4 = 67 pF, CL1 = 112
pF, CL2 = 69 pF and C5 = 43 pF were given.
Fig. 11 shows the simulated frequency response of the low-pass
filter with cutoff frequency of 110 kHz. Fig. 12 shows the transient
response of the low-pass filter with 10 kHz input signal. The THD
of the output signal Vout is 0.032%.
5
Conclusion
This paper presents a low-voltage low-power new CMOS structure
for the fully differential difference transconductance amplifier. The
circuit employs the QFG technique to achieve a simple CMOS
topology and class AB output stages. The voltage supply of the
FDDTA is 0.6 V and the static power consumption is 40 µW. The
simulation results of the proposed circuit and the example of
applications show the attractive features of this active element.
4.3 Simulation results of the FDDTA-based fifth-order elliptic
low-pass filter
6
The FDDTA-based fifth-order Elliptic low-pass filter in Fig. 5b
was simulated. As an example design, Rt1 = Rt2 = Rt3 = Rt4 = Rt5 =
Research described in this paper was financed by the Czech
Science Foundation under grant no. P102-15-21942S and by the
78
Acknowledgments
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
National Sustainability Program under grant LO1401. For the
research, infrastructure of the SIX Center was used.
Fig. 9 Steady-state waveforms of the quadrature oscillator output voltages
Fig. 10 Spectra of the quadrature oscillator output voltages
Fig. 11 Simulated frequency responses of the elliptic low-pass filter
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
79
Fig. 12 Transient response of the elliptic low-pass filter at 10 kHz
7
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
80
References
Sackinger, E., Guggenbuhl, W.: ‘A versatile building block: the CMOS
differential difference amplifier’, IEEE J. Solid-State Circuits, 1987, SC-22,
pp. 287–294
Huang, S.C., Ismail, M., Zarabadi, S.R.: ‘A wide range differential difference
amplifier: a basic block for analog signal processing in MOS technology’,
IEEE Trans. Circuits Syst. II, 1993, 40, pp. 289–300
Mahmoud, S.A., Soliman, A.M.: ‘The differential difference operational
floating amplifier: a new block for analog signal processing in MOS
technology’, IEEE Trans. Circuits Syst. II, 1998, 45, pp. 148–158
Mahmoud, S.A., Soliman, A.M.: ‘New CMOS fully differential difference
transconductors and application to fully differential filters suitable for VLSI’,
Microelectron. J., 1999, 30, pp. 169–192
Khateb, F., Bay Abo Dabbous, S., Vlassis, S.: ‘A survey of non-conventional
techniques for low-voltage, low-power analog circuits design’,
Radioengineering, 2013, 22, pp. 415–427
Khateb, F., Vlassis, S.: ‘Low-voltage bulk-driven rectifier for biomedical
applications’, Microelectron. J., 2013, 44, pp. 642–648
Monsurrò, P., Pennisi, S., Scotti, G., et al.: ‘Exploiting the body of MOS
devices for high performance analog design’, IEEE Circuits Syst. Mag., 2011,
11, pp. 8–23
Khateb, F., Kumngern, M., Vlassis, S., et al.: ‘Sub- volt fully balanced
differential difference amplifier’, Circuits Syst. Comput. J., 2015, 24, pp.
1550005-1–1550005-18
Kulej, T.: ‘0.4-V bulk-driven operational amplifier with improved input
stage’, Circuits Syst. Signal Process., 2015, 34, pp. 1167–1185
Khateb, F., Kumngern, M., Vlassis, S., et al.: ‘Differential difference current
conveyor using bulk-driven technique for ultra-low-voltage applications’,
Circuits Syst. Signal Process., 2014, 33, pp. 159–176
Raikos, G., Vlassis, S.: ‘0.8 V bulk-driven operational amplifier’, Analog
Integr. Circuits Signal Process., 2010, 63, pp. 425–432
Raikos, G., Vlassis, S., Psychalinos, C.: ‘0.5 V bulk-driven analog building
blocks’, AEU – Int. J. Electron. Commun. J., 2012, 66, pp. 920–927
Raj, N., Singh, A.K., Gupta, A.K.: ‘Low-voltage bulk-driven self-biased
cascode current mirror with bandwidth enhancement’, Electron. Lett., 2014,
50, pp. 23–25
Kulej, T., Khateb, F.: ‘Bulk-driven adaptively biased OTA in 0.18 μm
CMOS’, Electron. Lett., 2015, 51, pp. 458–460
Vlassis, S., Khateb, F.: ‘Automatic tuning circuit for bulk-controlled subthreshold MOS resistor’, Electron. Lett., 2014, 50, pp. 432–434
Kulej, T., Khateb, F.: ‘0.4-V bulk-driven differential-difference amplifier’,
Microelectron. J., 2015, 46, pp. 362–369
Khateb, F.: ‘Bulk-driven floating-gate and bulk-driven quasi-floating-gate
techniques for low-voltage low- power analog circuits design’, AEU Electron.
Commun. J., 2014, 68, pp. 64–72
Khateb, F.: ‘The experimental results of the bulk-driven quasi-floating-gate
MOS transistor’, AEU Electron. Commun. J., 2015, 69, pp. 462–466
Khateb, F., Kubánek, D., Tsirimokou, G., et al.: ‘Fractional-order filters based
on low-voltage DDCCs’, Microelectron. J., 2016, 50, pp. 50–59
Kubánek, D., Khateb, F., Tsirimokou, G., et al.: ‘Practical design and
evaluation of fractional-order oscillator using differential voltage current
conveyors’, Circuits Syst. Signal Process., 2016, 35, pp. 2003–2016
Khateb, F., Kumngern, M., Kulej, T.: ‘1-V inverting and non-inverting losertake-all circuit and its applications’, Circuits Syst. Signal Process., 2016, 35,
pp. 1507–1529
Khateb, F., Vlassis, S., Kumngern, M., et al.: ‘1 V Rectifier based on bulkdriven quasi-floating-gate differential difference amplifiers’, Circuits Syst.
Signal Process., 2015, 34, pp. 2077–2089
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
[32]
[33]
[34]
[35]
[36]
[37]
[38]
[39]
[40]
[41]
[42]
[43]
Khateb, F., Lahiri, A., Psychalinos, C., et al.: ‘Digitally programmable lowvoltage highly linear transconductor based on promising CMOS structure of
differential difference current conveyor’, AEU – Int. J. Electron. Commun.,
2015, 69, pp. 1010–1017
Lopez-Martin, A., Ramirez-Angulo, J., Carvajal, R., et al.: ‘Compact class
AB CMOS current mirror’, Electron. Lett., 2008, 44, pp. 1335–1336
Lopez-Martin, A.J., Angulo, J.R., Carvajal, R.G., et al.: ‘Micropower high
current-drive class AB CMOS current-feedback operational amplifier’, Int. J.
Circuit Theory Appl., 2010, 39, pp. 893–903
Lopez-Martin, A.J., Acosta, L., Alberdi, C.G., et al.: ‘Power-efficient analog
design based on the class AB super source follower’, Int. J. Circuit Theory
Appl., 2012, 40, pp. 1143–1163
Gupta, M., Pandey, R.: ‘Low-voltage FGMOS based analog building blocks’,
Microelectron. J., 2011, 42, pp. 903–912
Gupta, M., Pandey, R.: ‘FGMOS based voltage-controlled resistor and its
applications’, Microelectron. J., 2010, 41, pp. 25–32
Madhushankara, M., Kumar Shetty, P.: ‘Floating gate Wilson current mirror
for low power applications’, Commun. Comput. Inf. Sci., 2011, 197, pp. 500–
507
Khateb, F., Khatib, N., Koton, J.: ‘Novel low-voltage ultra-low-power DVCC
based on floating- gate folded cascode OTA’, Microelectron. J., 2011, 42, pp.
1010–1017
Kumngern, M., Khateb, F.: ‘Fully differential difference transconductance
amplifier using FG-MOS transistors’. Int. Symp. Intelligent Signal Processing
and Communication Systems (ISPACS), 2015, pp. 337–341
Lopez Martin, A.J., Carlosena, A., Ramirez-Angulo, J.: ‘Very low voltage
MOS translinear loops based on flipped voltage followers’, Analog Integr.
Circuit Signal Process., 2004, 40, pp. 71–74
Kumngern, M., Khateb, F., Dejhan, K., et al.: ‘Voltage-mode multifunction
biquadratic filters using new ultra-low-power differential difference current
conveyors’, Radioengineering, 2013, 22, pp. 448–457
Khateb, F., Jaikla, W., Kumngern, M., et al.: ‘Comparative study of sub-volt
differential difference current conveyors’, Microelectron. J., 2013, 44, pp.
1278–1284
Chatterjee, S., Tsividis, Y., Kinget, P.: ‘0.5-V analog circuit techniques and
their application in OTA and filter design’, IEEE J. Solid-State Circuits, 2005,
40, pp. 2373–2387
Razavi, B.: ‘A study of phase noise in CMOS oscillators’, IEEE J. Solid-State
Circuits, 1996, 31, pp. 331–343
Zhang, S., Li, A., Han, Y., et al.: ‘Temperature compensation technique for
ring oscillators with tail current’, Electron. Lett., 2016, 52, pp. 1108–1110
Khumsat, P., Worapishet, A.: ‘A 0.5-V R-MOSFET-C filter design using
subthreshold R-MOSFET resistors and OTAs with cross-forward commonmode cancellation technique’, IEEE J. Solid-State Circuits, 2012, 47, pp.
2751–2762
Prommee, P., Dejhan, K.: ‘An integrable electronic-controlled quadrature
sinusoidal oscillator using CMOS operational transconductance amplifier’,
Int. J. Electron., 2002, 89, pp. 365–379
Schaumann, R.: ‘Continuous-time integrated filters’, in Chen, W.-K. (Ed.):
‘The circuits and filters handbook’ (CRC Press and IEEE Press, New York,
1995)
Tan, M.A., Schaumann, R.: ‘A reduction in the number of active components
used in transconductance grounded capacitor filters’. Proc. IEEE Int. Symp.
Circuits and Systems, Louisiana, USA, 1990, pp. 2276–2278
Wyszynski, A., Schaumann, R.: ‘Using multiple-input transconductors to
reduce number of components in OTA-C filter’, Electron. Lett., 1992, 28, pp.
217–220
Lehmann, T., Cassia, M.: ‘1-V power supply CMOS cascode amplifier’, IEEE
J. Solid-State Circuits, 2001, 36, pp. 1082–1086
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
[44]
[45]
Grech, I., Micallef, J., Azzopardi, G., et al.: ‘A low voltage wide-input-range
bulk-input CMOS OTA’, Analog Integr. Circuits Signal Process., 2005, 43,
pp. 127–136
Ferreira, L.H.C., Pimenta, T.C., Moreno, R.L.: ‘An ultra-low-voltage ultralow-power CMOS miller OTA with rail-to-rail input/output swing’, IEEE
Trans. Circuits Syst. II, Express Briefs, 2007, 54, pp. 843–847
IET Circuits Devices Syst., 2018, Vol. 12 Iss. 1, pp. 73-81
© The Institution of Engineering and Technology 2017
[46]
Rezaei, F., Azhari, S.J.: ‘Ultra low voltage, high performance operational
transconductance amplifier and its application in a tunable Gm-C filter’,
Microelectron. J., 2011, 42, pp. 827–836
81