Florida A&M University
Electronic Engineering Technology
EET4166 Electronic Design II
A. Khawand
Sequential Circuits
Khawand_EET_Lecture_Template.pptx
Revision 08/13/2019
Sequential vs. Combinational Logic Circuits
Sequential Logic
In digital circuit theory, sequential logic is a type of logic circuit whose output depends
not only on the present value of its input signals but on the sequence of past inputs, the
input history as well. This is in contrast to combinational logic, whose output is a
function of only the present input.
Synchronous sequential logic
Nearly all sequential logic today is clocked or synchronous logic. In a synchronous circuit,
an electronic oscillator called a clock (or clock generator) generates a sequence of
repetitive pulses called the clock signal which is distributed to all the memory elements
in the circuit. The basic memory element in sequential logic is the flip-flop. The output
of each flip-flop only changes when triggered by the clock pulse, so changes to the logic
signals throughout the circuit all begin at the same time, at regular intervals,
synchronized by the clock.
The output of all the storage elements (flip-flops) in the circuit at any given time, the
binary data they contain, is called the state of the circuit. The state of a synchronous
circuit only changes on clock pulses. At each cycle, the next state is determined by the
current state and the value of the input signals when the clock pulse occurs
Sequential Logic Circuit Example
Binary Counter
The JK Flip-Flops below are cascaded together to form a 4-bit binary counter (0-15)
CLK
CLK
Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Q2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
Sequential Logic Circuit Example
BCD Counter
With additional logic a binary counter can be made
to count to a certain number and reset. We can
convert the previous counter (0-15) to BCD counter
(0-9), by adding a single NAND Gate. The gate goes
low when both Q3 and Q1 go to 1 (Decimal 10),
resetting count to 0.
# Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
RESET
First time Q3 & Q1 = 1
Sequential Logic Circuit Example
Frequency Divider Example
Certain circuits require a high-frequency input clock and possibly slower internal sub-system clocks. JK Flip-Flops can be cascaded to
divide the input frequency into 1/2, 1/4 , 1/8, etc…
Logic Analyzer
Q3
FREQ_IN/16
1 KHz
Q2
FREQ_IN/8
2 KHz
Q1
FREQ_IN/4
4 KHz
Q0
FREQ_IN/2
8 KHz
FREQ_IN
VCC
1
Q0
5.0V
Q1
Q2
7
2
~2PR
11
10
2Q
~2Q
~1PR
2J
9
2CLK
6
2K 12
~2CLR
8
7
15
14
1Q
~1Q
~2PR
1J
4
1CLK
1
1K 16
~1CLR
74LS76N
U2B
3
11
10
2Q
~2Q
~1PR
2J
9
2CLK
6
2K 12
~2CLR
74LS76N
U2A
8
Q3
2
15
14
1Q
~1Q
1J
4
16 KHz
1CLK
1
FREQ_IN
1K 16
~1CLR
74LS76N
U1B
3
V1
16kHz
5V
74LS76N
VCC
F
C Q T
5.0V
R1
2.2kΩ
S1
U1A
Key = C
XLA1
Adjustable Frequency Divider
Frequency Divider
The previous example illustrates how simple it is to divide a frequency by numbers that are multiples of 2 (1/2, 1/4, etc.…). However, there
are times when multiples of 2 division is not applicable. The circuit below allows division by a number x, where x ranges from 1 to 15 (1/3,
1/5, 1/10, 1/12, etc…), using a 4-bit binary counter. Division by larger numbers can be easily achieved by adding more bits to the counter.
Input
Clock
Divider Output
CLK Frequency / 5
Divisor
Selection
(X=5)
Input
Clock
Divider Output
CLK Frequency / 5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5