INFORMATION AND COMMUNICATIONS UNIVERSITY
SCHOOL OF ENGINEERING
DEPARTMENT OF ELECTRICAL/ELECTRONICS
DUE ON 21ST MARCH 2022
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Q1. Design three versions of the combinational circuit those input is a 4-bit
number and whose output is the 2' complement of the input number. for
each of the following cases.
(a) The circuit is a simplified two-level circuit. plus, inverters as needed for the input
variables
(b) The circuit is made up of four identical two input, two output cells. One for each bit.
The cells are connected in cascade, with lines, similar to a carry between them. The
value applied to the right most carry bit is 0,
(c) The circuit is redesigned with carry look ahead-like logic in order to speed up the circuit
in part (b) for use in larger circuits with 4n input bits.
20 marks
Q2. (a) with the aid of well labelled diagrams and examples, explain the working of the
following parameters.
(i)
(ii)
(iii)
(iv)
(v)
Multiplexer
Decoder
Full Adder
Parallel Adder
Comparator
20 marks
Q3. Show how a five bit 11011 binary number can illustrated in the five-bit serial in –
parallel out shift register.
20 marks
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Q4. (a) (i) What is race around problem in flip flop?
(ii) Draw the circuit diagram of a master slave SR flip flop and draw its truth table.
(b) implement the following each in a multiplexer. Y = ∑ ( 2, 4 7,12)
(c) (i) Explain what is meant by cascading an IC’s circuit
(ii) show how the 74LS83 circuit is cascaded
(d) examine the truth table of the half subtractor?
(e). Show symbol, data selection table and truth table of a 4 x 1 MUX.
20 marks
Q5. (a) (i) Given the 16 bit operand 00001111 10101010, what operation must be performed
and what operand must be used
(a) to clear all even bit positions to 0? (assume bit positions are 15 through 0 from left to
right)
(b) to set the leftmost 4 bits to 1?
(c) To complement the centre 8 bits
(b) Construct a 64 x 5 multiplexer
(c)
(i) State what is meant by the modulus of a binary counter
(ii) Differentiate between an asynchronous and synchronous binary counter
20 marks
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