DesignCon 2020
Jitter Measurements with
Decision Feedback Equalizer
Kalev Sepp, Signal Integrity Consultant for VESA
Sepson Analytics LLC
kalev24@gmail.com
John Calvin, Senior Strategic Planner
IP Wireline Solutions
Keysight Technologies
john.calvin@keysight.com
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Abstract
Advanced equalization consisting of CTLE and DFE is needed for current and future
generations of serial data standards to compensate for loss and maintain required bit error
rate. The jitter decomposition methodology that emerged few decades ago was the first
attempt to better understand the source of timing variations and effect on link
performance. While such analysis after CTLE is straightforward, measuring jitter after
DFE still is not fully understood or standardized. The paper will discuss models and
practical measurement considerations for jitter measurements after DFE as well as
implications for transmitter compliance testing in various standards.
Author(s) Biography
Dr. Kalev Sepp specializes in high-speed serial data standards development, related
measurements, signal processing and compliance testing. Until 2017 he worked as a principal
engineer with Tektronix developing signal integrity analysis algorithms and compliance
testing software. While member of various standards committees, including PCI-SIG, USBIF, and VESA, he contributed to respective electrical and test specifications. Currently, he
works as a signal integrity consultant for Video Electronics Standards Association (VESA)
developing compliance testing methodology and signal integrity analysis tools. Kalev has
multiple patents related to high speed signal measurements and is a co-author of a book.
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Introduction
Jitter measurements have inspired electronics and signal integrity engineers for decades.
Accurate timing of events in digital electronics is as inherent as a beat and pitch in music.
Accurate timing of signal transitions is necessary for getting correct information from a
source to target, from transmitter to receiver - the foundation for our digital life.
In practice, all components tend to have practical limitations and timing uncertainty. All
link designs start with a budget that attempts to establish reasonable limits on uncertainty.
This is important for viability of the ecosystem as well as technical and economic
success. This paper gives an overview of how various dimensions of the budget interact,
focusing on timing variations i.e. jitter. Special focus is on the jitter related to decision
feedback equalizer that has become common in contemporary designs. In link budgeting
and compliance testing a behavioral DFE is used that is implemented as a software
function. The actual hardware design has an additional freedom for implementation, but it
still shall be constrained to the budget established by the behavioral equalizer. However,
specific implementations can affect jitter interpretation and measurements. Correlation
between the hardware and behavioral DFE is important as well as between different test
solutions. Jitter for PAM4 signals is also discussed where several new challenges emerge.
The material is illustrated with animations that can be fully experienced at the DesignCon
conference presentation.
Loss and Jitter Budget
As data rates increase the channel loss becomes a dominant design challenge, and a jitter
source. Since channel loss causes inter-symbol interference a loss budget is established
for major components in the link. Similarly, all active components have intrinsic timing
variations that need to be taken into account establishing another budget. The budget
breakdown is important from the perspective of interoperability as we provide framework
for various vendors to build components.
Figure 1. Typical Serial Data Link
Jitter is commonly defined as a time deviation of significant events from their ideal time
of occurrence. In digital signals the significant events are edge transitions. For receivers
the bit time, time from an edge to another edge is even more important. That is the time
when slicing or determination of the bit value is made. Since the signal is relatively static
at that time, there is no easy way to relate any event to it. Hence, the clock recovery is
performed by using signal edges and applying a Phase-Locked Loop (PLL) circuitry or
software.
The time between the edge before and the edge after can be considered as a margin and
determined from the eye diagram as an eye opening.
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For a link with an external clock, its edges may be aligned to different regions of the data
signal (bit center) that need to be taken into account.
Correlated Jitter
The loss in packages, board traces, connectors, cables is a major design limitation.
Frequency dependent loss causes Inter-Symbol Interference (ISI). In most current links
the eye is closed at the input of the receiver, meaning that we have exceeded the one unit
interval budget without even considering the intrinsic loss and additional ISI in the
receiver. Fortunately, the ISI can be compensated with equalization as it is correlated to
the data pattern. This can be done both on the transmitter side as well as at the receiver.
Obviously, at the receiver we must be able to determine the data pattern to be able to
compensate for the large loss.
Figure 2 Serial Link Budget for Data Dependent Jitter
The primary reasons for frequency depend loss are the same that cause insertion loss [5]
• Losses in packages, cables and boards
• Reflections
• Noise and crosstalk
• Mode conversion
In addition, the Tx equalization itself introduces data dependent jitter due to changes in
the waveform shape.
Uncorrelated Jitter
Uncorrelated timing variations that are independent of the bit pattern can be divided into
deterministic and random. This jitter cannot be compensated except low frequency
wander or periodic jitter that will be tracked by clock recovery. The correlated and
uncorrelated jitter budgets are not independent. If we have more uncorrelated jitter, the
sensitivity to correlated jitter (ISI) increases and vice versa. Signal amplitude noise also
affects the recovery, some translates into timing jitter (AM/PM conversion) and some
increases the chance for errors and error propagation that is characteristic of DFE.
Hence, the sum of all uncorrelated jitter components shall not exceed unit interval (UI).
The main contribution comes from the transmitter. The passive cable contributes directly
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very little, except the effects of crosstalk that is mostly associated with connectors. The
amount of uncorrelated jitter in the receiver can be quantified only by receiver sensitivity
testing. In such testing a signal with prescribed jitter content is created by test equipment,
typically a Bit-Error-Rate-Tester (BERT), and applied at the input of the receiver.
Receiver’s ability to receive incoming data correctly is determined by loop-back or some
other type of error counter.
Figure 3 Serial Link Budget for Uncorrelated Jitter
For interoperation and compliance testing two test points are defined where budgets are
checked with jitter and eye measurements. To distinguish between different types of jitter
the deterministic and random jitter models and decomposition methods were introduced
nearly 2 decades ago. This helps to identify the sources of timing variations and estimate
the effect on the receiver. Separating jitter measurements into correlated vs uncorrelated
is useful for links with higher loss budgets.
The loss budget determines the requirements for equalization – the compensation
required to offset the effects of ISI. The suggested equalization types for a given insertion
loss are given in Table 1 [5].
Loss of max attenuation
Required receiver
-10 dB
No equalization
-15 dB
CTLE
-25 dB
CTLE and DFE
-36 dB
Advanced CTLE and DFE
Table 1 Required Equalization for Given Insertion Loss
There are other budgets like power and finance that serial link architects and signal
integrity engineers have to take into account. More complexity in the equalizer translates
into higher cost in the design as well as in the operation of such links.
Equalizers and Optimization
The standards that specify equalization check the budgets with equalization for a simple
reason. While TP2 can be usually checked directly, at TP3 the eye is usually closed as
shown above in the discussion of correlated jitter budgets.
Besides dealing with compensation of frequency dependent loss, the equalizers have to
deal with variations of such loss – the length of cable, variations in sources and sinks.
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This provides flexibility to component designers, manufacturers, integrators, as well as
the users. A typical equalizer consists of automatic gain control, continuous-time linear
equalizer and decision feedback equalizer shown in Figure 4
Figure 4. Typical Equalizer Diagram
Usually a range of CTLE curves are specified as well as the DFE tap range for d. The
best combinations of these are chosen to determine transmitter performance through
measurements. In measurements we typically use optimization for specific conditions. In
real operation, an adaptation may be used that adjusts receiver parameters as the link
conditions change. When variations grow above certain level, the link may need
retraining.
Figure 5 Example CTLE Curves for 20Gbps Link
The optimization considerations were covered in [1] with more detail. Here is a summary
of key conclusions. Optimization can be performed in sequential (cascaded) manner
where CTLE is optimized first and then optimum DFE taps are found. However, this may
not yield the global optimum. The combined optimization where all combinations of
CTLE gains and DFE tap values are searched can give a global optimum. The DFE
considerations paper [1] proposes a segmented eye rendering technique that allows to
find optimum DFE eye and associated measurements based on CTLE eye diagrams.
Different standards take a different approach in this regard.
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Jitter measurements after CTLE
Tx equalization and CTLE at the receiver affect the waveform shape and jitter analysis
applies in the same way as with any waveform. It is expected that correlated jitter is
reduced as the optimal CTLE DC-gain is applied compared to any other CTLE. With
suboptimal CTLE the eye may be closed that makes the jitter measurements invalid.
As the correlated jitter is reduced in the CTLE, the uncorrelated jitter usually remains the
same. As the correlated and uncorrelated components are not necessarily orthogonal or
stationary, the jitter separation algorithms may not be able to distinguish them with high
accuracy.
Before focusing on jitter measurements with DFE different implementation options are
covered that influence jitter methodology and interpretation of measurement results.
Behavioral DFE Implementation
In most common implementation we are dealing with feedback signal from the slicer that
adds or subtracts voltage from the incoming signal. One can think of this as a little source
in the receiver with associated signal properties like bandwidth and timing compared to
the input. Jitter and eye measurements would be defined for the point after the summing
as showing in Figure 6.
Figure 6. Measurements after DFE
The waveform after DFE with ideal adjustment (bandwidth and no delay) is shown in
Figure 7.
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Figure 7. Waveforms After Nominal DFE
While the DFE feedback introduces shifts in the waveform, the edge timing variations i.e.
jitter can still be visualized as a variation of edge crossing around the recovered clock.
As data rates increase the required feedback loop has to be really fast. To properly apply
the DFE feedback the compensating signal has less than 1 UI delay before applied to the
following bit slicing. For jitter measurements we need to apply this feedback before the
next the edge occurrence. While in the software implementing the behavioral equalizer it
doesn’t matter, it creates complication in actual chip hardware increasing power
requirements and introducing more noise. To alleviate these concerns, a parallel and/or
interleaved architecture is deployed. For a single tap DFE one can think of this as having
two separate slicers with different thresholds. This eliminates the need for adding the
DFE feedback signal and concern about delay and bandwidth. This circuit will only
consider slicing results from one of the slicers depending on the previous bit. Note that
the signal to noise ratio may suffer as the signal is split in half. This method is sometimes
referred in the literature as loop-unrolled implementation of DFE.
Figure 8. Unrolled DFE Implementation for Measurements and Eye Rendering
As the slicer threshold is modified the jitter is also measured at different voltage levels.
As the thresholding moves away from the center more AM/PM conversion effects and
sensitivity to vertical noise are included. By combining the eye diagram from two slicers
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we get a larger eye opening, reducing the data dependent jitter. However, jitter
measurements are not necessarily consistent due to combinations of two different level
threshold crossings. For rise/fall time symmetrical signals this may be reasonable
assumption.
The loop-unrolled DFE eye rendering is described in Figure 9. The figure shows 2 rows
of eye diagrams, corresponding to two slicers in 1-tap unrolled DFE. The first eyes in the
first column on the left are identical, rendered after CTLE. The signal is split into two eye
diagrams, one vertically shifted up and the other one down representing the slicing at
different levels (second column of eyes). This is equivalent to change in the slicing
threshold.
This shift clearly reduces margins as one of the eye opening gets close to the threshold.
However, if unfavorably latched bits are ignored on respective side, the eye opening is
improved. This is shown on the third column of eyes. The combination of two eye
diagrams produces an eye where all bits are present and eye margins can be evaluated.
The last column represents the combined eye and is duplicated for comparison. See also
more detailed description and optimization method in the last years DesignCon paper [1].
Figure 9 Unrolled DFE Eye Diagram Formation
The summary of different DFE eye rendering methods is given in Figure 10 and Table 2.
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Figure 10. Comparison of Nominal (left) and Unrolled (right) DFE Eye Diagram
Nominal DFE Interpretation
• Humps
• Symmetrical vertically and
horizontally
• Crossings are identical
• Output can be represented as a
waveform
• Eye is not shifted wrt recovered clock
(depends on DFE feedback delay)
• Jitter is calculated notmally, affected
by discontinuities
Unrolled DFE Interpretation
• No humps
• Asymmetrical in horizontal direction
• Crossings are not identical
• Output cannot be represented as a
single waveform
• Eye is shifted wrt CTLE recovered
clock (can be compensated)
• Jitter is not well defined
Table 2. Differences Between Nominal and Unrolled DFE Implementation
Unrolled DFE implementation may have additional benefits for link performance
evaluation. For example, if both slicers yield consistently the same logical output it is
easy to see that the link has a lot of margin, otherwise the opposite it true. This
information can be used for link training and adaptation.
DFE eye diagrams with multiple taps have the same properties except the feedback
signals are combined from multiple previous bit slicers. For unrolled implementation the
signal is split into 2^n slicers where n is the number of taps. The combination logic is
extended accordingly.
In practice, combinations of the two methods have been implemented where first one or
two taps are unrolled and for higher taps nominal feedback adjustment is performed.
Since the higher taps are usually smaller the DFE adjustment is smaller and less subject
to bandwidth and power concerns.
Jitter Measurements with DFE
Jitter in the Decision Feedback Equalizer has always been difficult to characterize. The
jitter depends on particular implementation and assumed model, as well as properties
often not expressed in standard documents. One may assert that since the bit polarity is
already determined in DFE, the jitter measurements after DFE are not useful. Difficulties
with jitter measurements have also forced many standards to just define eye width
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requirements. However, many standards define budgets assuming DFE and therefore eye
diagrams and jitter measurements after DFE are necessary for confirmation. A general
condition for jitter analysis is that clock recovery can distinguish bit boundaries –
determine the ideal edge crossing time. An exception to this is a study of low frequency
jitter analysis that CDR is not supposed to track.
The jitter should be evaluated in the context of horizontal eye opening. The jitter
impinging on the latch is the sum of left and right eye closure. The sum of jitter and
horizontal eye opening must sum to 1 UI. This applies both to measured values as well as
extrapolated TJ@BER and EW@BER, given the target BER value is the same.
𝐽𝑖𝑡𝑡𝑒𝑟 = 𝑈𝐼 − 𝐸𝑊
Keep in mind that the objective is to evaluate the transmitted signal at TP3 in the help of
the behavioral receiver. The actual receiver performance is not included in this
measurement. The actual receiver also works on signal at the receiver latch, including
additional loss in the receiver PCB and package.
Using the context of control system, measuring jitter is analogous to determining stability
margins in the closed-loop system. It is necessary condition that the system is stable i.e.
the eye is open and clock recovery is working properly.
Jitter with nominal DFE
For nominal DFE implementation where single-valued waveform exists traditional jitter
analysis can be applied. Due to application of feedback signal the deterministic and
random decomposition may not yield reliable results. However, the measurement of
residual ISI is valuable in estimating the effectiveness of the equalizer. While DFE
should reduce the amount of correlated jitter, the feedback signal may add some
depending on properties discussed above.
Jitter with unrolled DFE
As observed on Figure 9 the threshold crossings on two eye diagrams (column 3) are at
different voltage level and the summary eye crossings on the left and right become
different as shown in Figure 11. These crossings could still be considered for timing
variation analysis but they don’t necessarily represent the timing margins for the latch.
The previous and next bits are sliced at different levels and closure in those eyes does not
reflect the BER or eye margins at the receiver.
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Figure 11. Jitter interpretation in unrolled DFE eye
From the unrolled DFE eye diagram in Figure 11 it is easy to see that
𝐸𝑊 + 𝑇𝐼𝐸𝑙𝑒𝑓𝑡 > 𝑈𝐼
𝐸𝑊 + 𝑇𝐼𝐸𝑟𝑖𝑔 ℎ𝑡 > 𝑈𝐼
The combinations of two distributions on the eye make the jitter decomposition difficult
and spectral methods not applicable. Tail-fit methods suffer from the tail uncertainty
(long tails). As a result, many standards define only eye opening requirements for
waveforms after DFE to avoid correlation issues. Test and measurement solution
providers have attempted to address this need for advanced jitter analysis with unrolled
DFE but repeatability and interpretation concerns have prevented full adoption.
Recent standards with highest data rates (e.g. 400G Ethernet, 56Gbd PAM4) are more
commonly switching to ADC based heavily interleaved equalizer design. These designs
make the DFE jitter even more abstract in the context of the receiver and link
performance. However, if an equivalent threshold of a slicer can be established for each
symbol, the DFE eye diagram can still be rendered giving some idea of link performance.
If an eye diagram can be rendered, some jitter analysis can be performed that is useful for
link performance evaluation.
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Lane Margining and Jitter measurements
Latest generations of links have introduced lane margining capability into the standard.
This is not to replace testing with dedicated test equipment but give ability to evaluate
link health, training and optimization, and provide other insight into device performance.
Lane margining is especially useful for links with repeaters where troubleshooting
segments between links will be very difficult without lane such feature.
This functionality clearly a relationship to jitter measurements. For example, the loopunrolled design may already give us eye height margin information from normal
operation i.e. whether both slicers agree or not. The non-destructive lane margining
requires parallel path that can give valuable eye and jitter margin information.
PAM4 Jitter
PAM4 signaling has been discussed at the DesignCon starting from the early 2000s.
While PAM4 relaxes the loss budget for a given data rate, it increases the noise (SNR)
requirements. Due to three eye openings the jitter measurements become much more
complicated. Some of the issues with interpretation and threshold variation discussed
with unrolled DFE implementation apply even without DFE. How can multiple results be
combined into smaller set of measurements that describe the signal and the success of
receiving it at expected BER? Can such a number be produced independent of receiver
architecture?
Figure 12 PAM4 Jitter Measurement Challenge Whiteboard Discussion
When applying DFE to PAM4 signals, it clearly adds complexity. For example, the
optimum thresholds may even vary as the equalization parameters are changed. Their
positioning with respect to eye centers becomes subjective and driven by competing
criteria (e.g. eye width vs eye height). It is easy to see that upper and lower eye-opening
shapes become distorted as in Figure 13.
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Figure 13 Comparison of PAM4 eye without (left) and with DFE (right)
Results of 56Gbd jitter measurements are given in Figure 14. These are obtained from a
BERT source with PRBS13Q pattern at 56GBd representing IEEE 802.3ck standard
PAM4 signal.
Figure 14 PAM4 Jitter Measurements for 112Gbps (56GBd) Signal with DFE
Figure 15 PAM4 Jitter Noise Results for 112Gbps (56GBd) Signal with DFE
It is easy to note the large number of results and the difficulty of finding the most critical
one limiting the design.
According to recent literature PAM4 SerDes designs use interleaved and parallel ADCbased receivers. It is important that jitter and eye margins are calculated in a fashion that
is most relevant to those designs.
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COM and TDECQ
Jitter measurements alone do not necessarily characterize the link and provide
authoritative assessment of link margins. Eye diagrams are a great tool for visual
inspection and understanding link quality subtleties, but they are hard for ranking or
comparison to specification limits. There has always been need to develop a single
measurement that gives us a easy way to specify and compare designs. COM, TDECQ
and other similar concepts are created to overcome this and compare actual hardware to
established etalon. These will take into account the initial budgets as well as specific
timing and amplitude uncertainties to produce a single margin number.
Nonetheless, a good understanding of various jitter components, their source and effect
on receiver is still valuable even when the operating margins or penalties are calculated.
Conclusions
This paper has covered various aspects of serial data link budgeting and jitter
measurements with decision feedback equalizer. Understanding jitter budgets is
important at all levels of serial link technology. For specification it is important to
establish reasonable balance between different components to achieve successful
ecosystem. For component vendors and equipment users it is important in ensuring
working products. Based on jitter budgets, test vendors have to provide reliable
measurement and compliance testing framework.
As most standards are closed-eye the behavioral or reference equalizer implementation is
required in transmitter and system evaluation. DFE optimization and implementation
details affect the jitter and other measurements that provide the most relevant link quality
and robustness information.
Various considerations and measurement results are discussed. There is often no single
right answer, different test solutions make different assumptions and take slightly
different approaches. Understanding these differences allows to create more robust
designs and test procedures, achieve better correlation, and lead to more successful
products.
References
[1] Kalev Sepp, “DFE Implementation and Optimization Considerations for Test and
Measurement”, DesignCon 2019
[2] Jitter analysis: The dual-Dirac model, RJ/DJ, and Q-scale, Ransom Stephens, Agilent
Technologies 2004, retrieved on 11/17/2019
[3] VESA DisplayPort (DP) Standard, Version 2.0, 26 June, 2019, www.vesa.org
[4] VESA DisplayPort 1.4a PHY Layer Compliance Test Specification (PHYCTS)
Revision1.0 27 July, 2018
https://www.keysight.com/upload/cmc_upload/All/dualdirac1.pdf, retrieved 11/17/2019
[5] Eric Bogatin, “Webinar: Lossy Interconnects and Insertion Loss”, bethesignal.com,
retrieved 11/6/2019
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