IL2218 Analog Electronics, advanced course 2010‐01‐14/BM Questions and problems for exercises and labs IL2218 Analog electronics, advanced course P3, 2009/2010 Requirements To pass the lab course: At least 50% of selected problems of each chapter shall be solved. At least 50% of simulation of selected problems of each chapter shall be simulated and with proper documentation. Solving and simulating more than 75 % of the problems in each chapter could, if it is well documented and discussed, raise the grade at a passed written exam one grading step. Exercise You shall be ready to show and explain the solutions during exercise. Lab You shall be ready to show and explain your simulations during lab. What is L? There is some inconsistency in the book about whether L means Leff or Ldrawn. In the text of the book L means Leff as declared on page 11. In the end of chapter problems L means the drawn length Ldrawn. Leff = Ldrawn – 2LD where LD is the overdiffusion. L=Leff shall be used in formula when solving problems. This means that if you have Ldrawn= 0.5 µm and LD= 0.08 µm the effective length is Leff= 0.5 ‐ 2⋅0.08 = 0.34 µm. This is valid for NMOS transistors specified by table 2.1. PMOS in table 2.1 has another value for LD. This is the way you shall handle this in the course. In formulas: W
W
means , i.e. we specify the electrical size of the transistor. L
Leff
In problem when specifying W
W
it means , i.e. we specify the geometrical size of the L
Ldrawn
transistor. Example, NMOS transistor specified by table 2.1 : If W 50 μ
W
50 μ
W 50 μ
=
in problems, use =
in hand calculations, use =
in simulations. LD L 0.5μ
L 0.34 μ
L 0.5μ
is specified in the SPICE model so it will give the same results. Chapter 2 Read the chapter first before answering questions and solving problems. Questions 1 The explanation of ”pinch off” in the book is maybe a little bit weak. Try to make a better explanation! How could there be a current in the channel if Qd(x) drops to zero at the drain end of channel? 2 Why is it to prefer NMOS transistors instead of PMOS in integrated amplifiers? 3 Explain how to characterize the MOS transistor in triode and saturation region. 4 Explain the following second order effects: a Body effect b Channel –length modulation c Subthreshold conduction 5 Explain all types of capacitances in the complete small signal model of the integrated MOS transistor. 6 How is the body effect and channel length modulation recognized in the transistor small signal model? Problems 2.1 + simulation 2.2 + simulation 2.3 2.4 + simulation 2.5 a, b, c 2.7 a + simulation 2.9 b + simulation 2.13 2.15 + simulation fT Chapter 3 Read the chapter first before answering questions and solving problems. Questions 1 Consider the common‐source amplifier stage in fig 3.3. In the text the small signal gain is explained in two ways. Try to write those explanations in your own words without using formulas. 2 In figure 3.8, what is the reason for using Vx and Ix? 3 Describe and compare different ways of loading the common‐source stage. 4 At mid page 57: Resolve the seemingly opposite trends suggested by (3.35) and 3.37). 5 Consider the Cs stage with source degeneration. Explain the advantages and disadvantages of using this configuration. 6 Explain why the common‐drain stage is called a source follower. 7 The source follower has two major drawbacks: nonlinearity and voltage headroom limitation. Explain why! 8 Compare the common‐gate, common‐source and common‐drain amplifier stage in respect to gain, input resistance and output resistance. 9 The cascode circuit is widely used. Explain the advantages of this circuit compared to the common‐source stage. Problems 3.1 + simulation 3.2 + simulation 3.3 a,b + simulation 3.4 + simulation 3.15 b,c,d + simulation 3.14 + simulation 3.20 3.23 Chapter 4 Read the chapter first before answering questions and solving problems. Questions 1 What advantages do we have by using differential signals in a system? 2 What is wrong in figure 4.3 b? 3 Why is the output Vout1‐Vout2 in figure 4.7b limited to ±RDISS? 4 Describe the two methods to derive the small signal gain (method I and method II) 5 Compare CM gain in formula 4.28 to the gain of the basic common source stage with source degeneration. 6 The gilbert cell is often used in radio frequency circuits as a multiplier (mixers, phase detector). Explain why the gilbert cell can operate as an analog voltage multiplier. Problems 4.4 + simulation 4.5 a, b, c (note: should be 50 mV in b) + simulation 4.6 + simulation 4.7 + simulation 4.14 4.18 Chapter 5 Read the chapter first before answering questions and solving problems. Questions 1 Why do we need current sources? 2 Why is ID poorly defined in a MOS transistor although VGS is precisely defined ? 3 Why is IREF precisely copied to IOUT in fig 5.5b? 4 Why is IREF not precisely copied to IOUT in fig 5.5b? 5 Explain the function of the cascode current mirror. Compare it to the simple current mirror. Why is it better? Any drawbacks? 6 Make an explanation in your own words, of the small signal gain in equation 5.32 based on how it is derived in section 5.3.2. Problems 5.2 + simulation 5.4 + simulation 5.7 + simulation 5.8 Chapter 6 Read the chapter first before answering questions and solving problems. Questions 1 A capacitor is connected from input to output of an inverting amplifier (Miller capacitance). What is the equivalent capacitance seen at amplifier input? output? 2 Explain the expressions of the poles at the input and output of the common‐source stage (fig 6.10). 3 Prove equations 6.16 and 6.17 4 Study the exact transfer function of the CS‐stage (equation 6.23). Compare the results of this to the node pole approximations (input and output poles, equation 6.18) 5 There is also a zero in the transfer function. Explain the meaning of that the zero is in the right half plane! 6 For the source follower the transfer function has two poles and one zero. a Explain the meaning of that the zero is in the left half plane. b Explain how to identify 6.43 from 6.42 c If Rs=0, then ω p1 =
gm
. Explain how to find this from fig 6.17 without CL + CGS
calculations. 7 Explain the expression for the poles associated with nodes A, X, Y in figure 6.25 (cascode stage). 8 Explain why the cascode stage performs better at high frequencies than the usual CS‐
stage. Problems 6.3 + simulation (small signal voltage gain, amplitude and phase) 6.4 + simulation 6.7a 6.11 Chapter 7 Read the chapter first before answering questions and solving problems. Questions 1 What is white noise? 2 Explain the physical origin and the type of power spectral density for a thermal noise b flicker noise 3 Two uncorrelated noise sources V1n= 0.1 µV and V2n= 0.2 µV are connected in series. What is the total noise voltage? 4 Explain the noise model of the MOS transistor. 5 Explain what is meant by input referred noise. Problems 7.1 7.2 7.4 7.5 Chapter 8 Read the chapter first before answering questions and solving problems. Questions 1 Using the notation of a simple feedback system in figure 8.4, define a open loop gain b loop gain c closed loop gain d feedback factor 2 Explain the gain desensitization in feedback systems. 3 Why are we interested to compute the loop gain? 4 Explain how the input resistance is affected by feedback. 5 Explain how the output resistance is affected by feedback. 6 Explain how the bandwidth is affected by feedback. 7 Describe how to analyze feedback amplifiers including the effects of loading Problems 8.1 + simulation 8.2 + simulation 8.3 8.5 8.10 + simulation 8.16 + simulation 8.17 + simulation Chapter 9 Read the chapter first before answering questions and solving problems. Questions 1 Define the concept “operational amplifier”. 2 Explain the following op amp design parameters a gain b small‐signal bandwidth c large‐signal bandwidth d output swing e linearity f offset g supply rejection 3 Compare the cascode op amps in figure 9.8 to the simple op amp topologies of figure 9.6. What are the advantages and disadvantages? 4 Compare the telescopic cascode op amps to the folded cascode op amp topologie. What are the advantages and disadvantages? 5 Explain the idea of gain boosting in operational amplifiers. 6 Explain why there is a need for common mode feed back in CMOS high gain operational amplifiers. 7 What is meant by slewing and slew rate in operational amplifiers? Problems 9.1 + simulation 9.6 + simulation 9.7 + simulation 9.16 (let R be the output resistance of current source ISS) 9.18 + simulation 9.19 + simulation Chapter 10 Read the chapter first before answering questions and solving problems. Questions 1 The stability of a feedback amplifier could be studied in two different ways. Describe which function to study when analyzing stability a in Bode plots b in root locus plot 2 How is gain margin defined? 3 Op amps usually need to be compensated so that the closed loop circuit is stable. Describe the two ways to achieve a frequency compensated op amp. 4 Describe the dominant pole compensation technique. How should the frequency of the dominant pole be chosen? 5 In two‐stage op amps with Miller capacitor compensation there could be a right‐half‐
plane zero. Explain why this could make the amplifier unstable in feedback configuration. 6 Explain how to move the right‐half‐plane zero into left‐half‐plane and make the closed loop amplifier stable. 7 Describe why a load capacitance could degrade the phase margin of an op amp in feedback configuration. 8 Why is the output voltage a linear function of time (constant slope, slew rate) if the op amp is in feedback configuration and has a step input voltage? Problems 10.1 10.3 10.5 + simulation 10.6 10.8 10.9 + simulation 10.11 + simulation