International Journal of Micro and Nano Electronics, Circuits and Systems, 3(1), 2011, pp. 55-59
LOW POWER CLASS AB OPERATIONAL TRANSCONDUCTANCE
AMPLIFIER FOR CAPACITIVE SENSORS
Akhil Babu1 & J.Grace Jency2
Department of ECE, Karunya University, Coimbatore, India
(akhilbabu.e@gmail.com1, gracegency@karunya.edu2)
Abstract: A low power OTA for a generic interface circuit of capacitive sensor is presented in this paper.
This circuit possesses flexibility and reduces the design cost of the interface circuit. The architecture consist
sensor readout circuitry followed by capacitance to voltage converter and a signal processor. This switched
capacitor interface works on lower clock frequency of 8 KHz destined for the low power consumption. The
capacitance to voltage conversion is accomplished using a class AB operational amplifier and correlated
double sampling. This technique provides an interface for broad range of capacitive sensors.
Keywords: Class AB; operational transconductance amplifier (OTA); low power.
1. INTRODUCTION
Interface architectures that developed so far
considered interface circuit and sensor as two
different entities. These approaches will increases
the parasitic elements, interconnection resistance
and signal loss. The hybrid chip architecture which
integrates a MEMS capacitive sensors and an
interfacing circuit is presented in this paper. The
paper is targeted for the low power applications
relying on battery for its power source. This design
will reduce the number of interconnections and
make the design more compact, more over
capacitive sensor will not draw current from the
supply unlike piezo resistive sensors. Interface
circuit is following a generic design [1] so it is
capable of sensing various quantities that could
make any deflections in the diaphragm. This type
of sensor finds its application in military, medicine,
and in automotive fields. Emerging market urges
for low cost, low power and more compact products.
Power dissipation is the major area of research for
last two decades. The sensor and interfacing being
considered as two separate modules in the existing
architecture increases the power consumption and
parasitic capacitance. Hybrid chip which is
described in this paper will address the power
dissipation problem. The power consumption will
be in the range of micro watts. The hybrid chip
reported in this paper is a significant development
of a single chip solution for the capacitive sensor
with interfacing circuit. Resulting outputs can be
directly fed to the micro controllers or micro
processor for further processing.
Rest of the paper is organized as follows. Firstly
we begin with a general discussion of capacitive
sensor and its electrical model. This will be followed
by architecture and basic operation of class AB OTA.
The result has been analyzed in section IV followed
by conclusion.
2. CAPACITIVE SENSOR
Capacitive sensors have acquired a wide acceptance
in the market compared to other sensing techniques.
This is because of the certain added advantages that
the capacitive sensors posses. The advantages
include high sensitivity, good DC response, low
temperature sensitivity and low power
consumption [2]. The main disadvantages include
parasitic elements and sensitivity to Electro
Magnetic Interference (EMI). The major problem to
be addressed here is the reduction of the parasitic
elements with low power consumption. The
interface circuit is intended for a differential
capacitive sensor which will have the linear relation
with change in capacitance to the change in voltage.
In this paper for the verification purpose capacitive
sensor is replaced by an electrical model [3].
Electrical model is given in the Figure 1. This simple
electrical model includes two parasitic capacitances
Cpar1 and Cpar2, sensing element Csen and Gpa the shunt
conductance in the electrical model [2].
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International Journal of Micro and Nano Electronics, Circuits and Systems
frequency noises. The new architecture restricts the
shunt leakage [6] to minimum while maintaining
low power and low frequency.
3.1. Capacitance to Voltage Converter
Figure 1: Electrical Model of Capacitive Sensor
3. ARCHITECTURE
Interface circuits are the inevitable part of capacitive
sensors. The parasitic elements present in the
capacitive sensor will be very high compared to the
sensed capacitance [4]. Capacitive sensors will also
be affected by the low frequency noises present at
the terminals. These reasons make the tight design
of the front end analog interface part necessary. In
this paper we present an architecture developed on
the basis of an idea proposed by W. Bracke et al.[5].
The architecture is given in the Figure 2. The
capacitive sensor is connected to the front end
analog block to reduce the effect of parasitic and
remove the low frequency noises.
The architecture given in Figure 2 shows sensor
as the initial block and then followed by a
capacitance to voltage (C-V) converter. This
interface is used for the suppression of the effect of
parasitic and noises. It is suited for broad range of
differential capacitive sensor whose differential
capacitance is proportional to differential voltage.
To maintain a low power profile switched
capacitance interfaces is selected which fires at 8
KHz. This frequency is set as a tradeoff between
power consumption and effective removal of
parasitic. As frequency is increased the power
consumption is increased. While lowering the
frequency, effects of parasitic capacitance and low
frequency noises will increase. The shunt
conductance element replaces the leakage charges
in the electrical model of the sensor.
All the above dealt issues are compromised by
the low power C-V convertor which utilizes a class
AB transconductance amplifier along with
correlated double sampling technique (CSD). This
circuit reduces the effect of the parasitic and low
The architecture of C-V is given in the Figure 3. This
circuit offers lower power and efficiently reduces
the parasitic effects represented by Cpar1 and Cpar2.
Switched capacitor cancels the effect of parasitic
elements [7]. The clock phases are divided into two,
sampling phase Φ1 and signal phase Φ2. Here Vp will
become a virtual ground and the charge stored in
the sensor capacitance C sen is transferred into
feedback capacitance Cf. In ideal charge transfer case
the output is given by the Vref(Csen/Cf). Practically
charge transfer will be imperfect owing to the charge
leakage through parasitic shunt conductance.
Reasons for leakage are response time of the
operational transconductance amplifier (OTA), DC
offset and finally the finite gain of the OTA.
The architecture given in the Figure 3 need
single reference voltage and measurement cycle to
determine the value of Csen. It uses the correlated
double sampling to purge the offset voltage of the
sensor interface. During sample phase the capacitor
Csam samples the offset voltage and in the successive
phase the stored value is subtracted from the
contemporary value.
The C-V converter uses class AB OTA shown in
Figure 4. The class AB operation will make the
circuit more efficient to reduce the leakages. As the
phase transition occurs, tail current of the OTA will
be boosted and fastens the charge transfer from the
sense capacitor C sen . Quiescent low level tail
current will be restored as the Vp reaches the virtual
ground.
To get an insight about the OTA it is necessary
to know that the circuit is based on the principle of
self-biased transistors combined in a common
source configuration. The circuit resembles to
symmetrical OTA except at the input stage and tail
current. Main modification of the present design is
that it uses a negative feedback mechanism. This
makes sure that the common source voltage of T1
and T2 is always forced to track the smaller of the
two voltages Va and Vb. When Vin+ is larger than Vinvoltage Vb is larger than Va which is coupled to the
internal feedback op-amp. The common source
voltage in this case is determined only by Vin-, the
device size of Ta and the constant bias current Ib.
Low Power Class AB Operational Transconductance Amplifier for Capactivie Sensors…
57
tracking. The stability of the feedback is retained
by the compensation capacitor formed by the gatesource miller capacitance. As dimension of the input
device increases, capacitance formed at gate source
increases proportionally. Device size also increases
current consumption and fast tracking response. So
an optimal class AB OTA is desired for our
particular low power interface.
In low power interface the power consumption
can be reduced by reducing the clock frequency.
Reduction in the frequency is limited by the
accuracy. Low frequencies makes CSD less effective
in reducing 1/f noise, degrades the system noise
performance added by the OTA and increases the
effect of electrostatic forces on the accelerometers
[8-9]. So as an optimal value clock frequency is
selected as 8 kHz.
Figure 2: Architecture of Capacitive Sensor Interface [5]
Figure 3: Correlated Double Sampling Scheme for C-V
Converter
The current boosting for input transistors
operated in weak inversion for small input voltage
range “Vin=Vin+-Vin- is given by
IM1
∆V
= exp ( in )
IM2
nUT
(1)
Where n is the weak inversion slope factor and
UT= (kT/q) is the thermal voltage. As the input
voltage increases to high values the input transistors
leaves the weak inversion mode. Input transistors
with larger (W/L) ratio improve the current
boosting.
When differential input voltage increases the
transistors will leave weak inversion and follows
the square law. The current through T1 is given by
IT 1 =
1
2
W 
* Kn 
 (Vin + – Vin − + ∆V )
2
 L T 1
Figure 4: Class AB OTA
4. SIMULATION RESULTS
Class AB op-amp shown in Figure 4 was modeled
using 0.18µm N-well CMOS technology. Op-amp
biased with a voltage of 1.8V.The measured offset
is found to be -3mV for a DC input voltage of 0V.
The OTA is designed to have a gain around 40 dB,
and obtained figure is given in Figure 6.
(2)
Where
DV = 2 I b / K n ( W / L )a
(3)
Internal feedback op-amps, op1 and op2, is given in
the Figure 5. Simple five transistor OTAs are used
as the op-amps to maintain low power and fast
Figure 5: Schematic of Negative Feedback op-amp Used in
OTA
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International Journal of Micro and Nano Electronics, Circuits and Systems
The offset of OTA is related to the gain and
given as Vin/A0, where A0 is called the DC gain of
the OTA and in this case it is 42dB with non
cascoded output stage. As the OTA is made to work
in the weak inversion mode the current boosting
will increase and power dissipation of the circuit
will reduce. The Figure 6 shows the closed loop gain
and bandwidth of the circuit. The gain as given
before it is measured as 42dB and the gain
bandwidth is found to be 423Khz. The phase margin
is found to be 71º for a load of 10pf. Here the
dominant pole is given by the load capacitance. As
we go on increasing the load capacitance the plot
will start to dropdown at still lower frequency. The
output stage got a significant effect in gain and
phase plot. Similarly if we lowers the load then the
band width can be improved. In the case of the OTA
the secondary poles are determined by the aspect
ratio of the transistors T3 and T4. The effect of miller
capacitance formed between the gate and the source
of the input transistors, will assist the OTA to linger
in stable operating condition. This capacitance will
act as compensation capacitance. If the output stage
is cascoded the gain will be many times higher. The
performance of the class AB OTA is shown in the
Table 1.
Figure 7 shows the relationship between Va, Vb
and Vs. To maintain the negative feedback intact the
Vs will follow Va or Vb whichever is smaller. Vs is
connected to the non inverting terminal and Va and
Vb to inverting terminal causing the output of the
feedback op-amp to pull its output voltage nearer
to negative supply rails when either of Va or Vb is
higher than V s. This operation explained above
guarantee the negative feedback in the circuit. The
Figure 8 shows the output swing of the circuit.
Similarly the current boosting of the circuit is found
to be 85 times the quiescent current. Output can
have a maximum swing of 2Vdd-2Vov if the supply
Table 1
Performance of Class Ab Ota
Technology
Supply voltage
DC gain
Unity gain frequency
Phase margin
Random offset
Current boosting (∆Vin=.4V)
Power dissipation
1.8V
42 dB
423 Khz
71º
-3mV
85
281µW
ranges from 1.8V to -1.8V.The output obtained from
the switched capacitor configuration is given in
Figure 9. The capacitor Csam samples the offset at
the output leads and cancels that from the present
Figure 7: Tracking of Vs over Va and Vb.
Figure 8: Output Voltage Swing of OTA
Figure 6: Closed Loop Response of Class AB OTA
0.18µm
Figure 9: Output of Switched Capacitor Interface
Low Power Class AB Operational Transconductance Amplifier for Capactivie Sensors…
value. This switched capacitance architecture is used
to flush out the low frequency noises and the effects
of parasitic capacitance. Effects of the parasitic
capacitance will be negligible in switched capacitor
architectures. Output will be ideally given by
Vref(Csen/Cf).
5. CONCLUSION
A low power class AB OTA used for the interface of
the capacitive sensors is presented in the paper. The
architecture given in the paper cancels the noise and
parasitic effects well above the requirement for
moderate level of accuracy (10bit). The class AB
OTA presented here is designed with 0.18µm
technology and current boosting up to 100 fold is
possible. The circuit uses a negative feedback to
maintain current boosting and low power profile.
The sensor interface works on 8 KHz frequency and
correlated double sampling operation removes the
effects of parasitic conductance.
ACKNOWLEDGEMENT
The authors would like to express their sincere
gratitude to Dr. A. Ravi Shankar for his dynamic
guidance and support in the preparation of
manuscript. The authors would like to extend their
gratitude to Mr. Manikandan for his suggestions in
development of the paper.
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