A Tracking Negative
Voltage Made Easy
By John Betten, Application Engineer,
Texas Instruments, Dallas
A simple circuit added to any synchronous-buck
converter generates a tracking negative output
that achieves good voltage regulation, low cost,
small area and high efficiency.
H
igh-speed servers, workstations and clock
distribution networks are applications that
require transistor-transistor logic (TTL) to
emitter-coupled logic (ECL) translators.
Differential ECL devices typically require
both a positive and negative output voltage. When the
input power is a positive dc voltage, several methods exist
to create the voltage inversion necessary for the negative
output voltage.
A charge-pump, inverting buck-boost and Cuk converter
are all possible topologies. Each requires a dedicated control
circuit for regulation. Except for the charge pump, multiple
components, such as an inductor, FET and diode, are
needed in each power stage.
The inverting charge pump is
a more compact solution, but
suffers from poor efficiency and
voltage regulation as the load is
increased.
Flybacks and other transformer design approaches are
also candidates. These approaches would only be selected if
justified by the need for other high-power output voltages
in the system. In such cases, the negative 5-V output would
be post-regulated via a linear regulator from a transformer’s
auxiliary winding. None of the approaches mentioned
combine the virtues of low-cost, high-performance and
small area. A simple solution described here can address
these shortcomings.
The dual synchronous-buck converter in Fig. 1 represents
a typical design solution for the positive 5-V output voltage
and a second system-defined output voltage, which in this
case is 3.3 V. The circuit within the highlighted box identifies
the additional components used to generate the negative
5-V output. The positive 5-V circuit operates as a standard
synchronous-buck converter, with the switching cycle
consisting of two parts.
During the first period of the switching cycle, the top
FET Q2A conducts and applies a voltage equal to VIN – VOUT
across inductor L1 pins 3-1. FETs Q2B and Q1 are off during
this time, and the negative 5-V output capacitor C2 supplies
all of the negative 5-V output current. C2 must be sized
appropriately to supply the negative 5-V current during
this period and keep the negative 5-V output ripple voltage
within the required specifications.
While Q1 is off, it must block a voltage equal to the
negative 5-V output voltage plus the voltage coupled across
the auxiliary winding of L1. With the 1-to-1 turns ratio of
L1, the Q1 blocking voltage is essentially equal to the input
voltage.
Differential emitter-coupled-logic devices typically
require both a positive and a negative output voltage.
Power Electronics Technology February 2006
During the second part of the switching cycle, the
controller switches the top FET Q2A off and the bottom FET
Q2B and Q1 on. The voltage on the inductor L1 pins 1-3
must reverse to maintain current flow in the same direction
(into the output). This puts a positive voltage on the “dot” of
the coupled inductor winding. The magnitude of the voltage
across L1 pins 1-3 is now clamped to a level equal to the output
voltage plus the relatively small voltage drop of Q2B.
Note that during the bottom FET Q2B conduction time,
current flows in a clockwise direction through the inductor
and the load, returning through the bottom FET Q2B and
the inductor. During this conduction phase, the coupled
inductor secondary winding, pins 2-4, has a voltage equal to
the voltage on pins 1-3, since both windings have an equal
number of turns. Since FET Q1 is on, current flows from
the secondary winding into the load as well as replenishing
the charge in C2.
22
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NEGATIVE VOLTAGE
J4
C23
68 pF
C18
1000 pF
R13
13.7 kΩ
C9
0.01 µF
C10
47 pF
VIN = 12 V
C13
0.1 µF
C15
0.022 µF
C16
0.01µF
C28
68 pF
C26
1500 pF
R6
10 kΩ
R4
34 kΩ
R17
20.5 kΩ
5V
R3
100 kΩ
R14
4.12 kΩ
R1
10 Ω
Q1
Si3446DV
1 µF
C20
1 µF 1 µF
3.3 V
2
1
negative 5 V
at 0.3 A
GND
C2
22 µF
5V
C21
10 µF
C7
22 µF
Q2:B
FCS6990A
C11
0.01 µF
R9
5.49 kΩ
R8
15.4 kΩ
C14
0.01 µF
R10
10 Ω
C19
4
3
L1
10 µH
C8
C27
R5
5.23 kΩ 150 pF
R16
100 kΩ
Q2:A
FCS6990A
R15
10 Ω
U3
TPS5124DBT
freq = 300 kHz
R2
1 kΩ
C29
10 µF
C24
180 pF
D3
MBR0530
INV1
LH1
FB1
OUT1_U
SS1
LL1
NC
OUT1_D
CT OUTGND1
NC
TRIP1
GND
VCC
REF
TRIP2
STBY1 VREF5
STBY2
VLSD
SCP OUTGND2
NC
OUT2_D
SS2
LL2
FB2
OUT2_U
INV2
LH2
D1
C1
0.1 µF BAS16
J3
C6 + C17
22 µF 100 µF
positive 5 V
at 2 A
GND
VIN = 12 V
C12
0.1 µF
Q3
FDS6694
R7
3.3 Ω
D5
MBR0530
Q4
FDS7788
C25
10 µF
C30
10 µF
3.3 V
L2
3.9 µH
C3
22 µF
J5
C4 +
C5
22 µF
100 µF
2
1
3.3 V at 7.5 A
GND
Fig. 1. Adding a minimal number of components (shown in the highlighted box) to this dual synchronous-buck converter provides a negative
output voltage.
The voltage present at the negative output is equal to the
inductor’s secondary voltage, minus FET Q1’s conduction
voltage drop and the inductor’s resistive drop. Selecting
an inductor with low winding resistance and a FET with
low on-resistance will minimize these voltage drops. The
result is less variation in the negative 5-V output as its load
increases. Minimizing the on-resistance of bottom FET Q2B
also improves the voltage regulation on the negative 5-V
output because this drop is proportional to the positive 5-V
output current.
It’s interesting to note that the higher the FET Q2B’s
voltage drop, the more negative the negative 5-V output
becomes. It is possible that the voltage drops of FETs Q2B
and Q1 can cancel each other out under certain positive 5-V
and negative 5-V output load conditions, resulting in perfect
output-voltage matching.
C41
CM2
Fig. 3. For the circuit shown in Fig. 1, inductor L1 currents were
measured on its primary winding (top trace, pin 3) and secondary
winding (bottom trace, pin 4) at full load. (Amplitude scale = 500
mA/div and time scale = 1 µs/div.)
Fig. 2. Measurements taken on the circuit in Fig. 1 reveal the gate voltage
waveform of Q1 (top trace) and the negative 5-V output voltage
(bottom trace). (Amplitude scale = 2 V/div and time scale = 1 µs/div.)
Power Electronics Technology February 2006
24
www.powerelectronics.com
NEGATIVE VOLTAGE
Since the secondary winding current is delivered in
The gate-drive voltage of Q1 is derived from the gatepulses, it places a larger burden on the output capacitors
drive voltage of the bottom FET Q2B, as both FETs operate
for the negative 5 V. It is not hard to see that, with a large
in-phase with each other. The peak-to-peak amplitude of
negative 5-V load current, the positive 5-V and negative 5-V
the bottom FET gate-to-source voltage is 5 V, as set by the
outputs would require excessively large output capacitors
controller. Capacitor C1 ac couples this switching signal, but
to maintain reasonable ripple voltages. This is why only
blocks its dc average level. Diode D1 conducts only during
light loading on the negative output—relative to the positive
a negative voltage swing, clamping Q1’s gate voltage to
output—is recommended.
0.7 V below the source pin and turning it off.
This circuit uses a Coiltronics DRQ127 coupled inductor,
During a positive voltage swing, the peak voltage will
which has a very low winding resistance and a high dc
now be 5 V greater than when it was off. This gives a positive
current rating. It comes in a standard-sized package that
gate-to-source voltage of approximately 4.3 V, turning Q1
on. The use of a MOSFET with a 2.5-V gateto-source threshold is necessary to ensure
that Q1 becomes fully enhanced. The use of
diode D1 allows nearly all the available drive
voltage amplitude (less one diode drop) to
be used for the positive-going gate-to-source
voltage.
Without D1, the positive-going gate-tosource voltage amplitude would vary with
duty cycle. Its lowest amplitude is when
the input voltage is greatest, and increasing
the likelihood that Q1 could not turn on
properly. The body diode of Q1 allows the
negative 5-V current to conduct through it
during the FET switching transition times
(and before Q1 fully turns on), but cannot
provide the low forward drop necessary for
good output regulation. N-channel devices
are utilized for Q1, allowing for lower RDS(ON)
values than p-channel devices, as well as
a much greater selection of commercially
available devices.
Fig. 2 shows FET Q1’s measured gate
voltage obtained with respect to ground
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in 2.5V to
in inductor L1’s primary and secondary
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additional output capacitors on the positive
5-V output in order to keep the outputripple voltage low.
DC/DC CONVERTERS
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25
Power Electronics Technology February 2006
NEGATIVE VOLTAGE
C24
Fig. 4. The positive 5-V (top trace) and negative 5-V (bottom trace)
output voltages of the circuit in Fig. 1 track closely at start up.
(Amplitude scale = 2 V/div and time scale =2 ms/div.)
-4.90
Positive 5 V at 0.5 A
Positive 5 V at 1 A
Positive 5 V at 1.5 A
Positive 5 V at 2 A
Output Voltage (V)
-4.95
-5.00
-5.05
-5.10
-5.15
0.00
0.05
0.10
0.15
0.20
Negative 5-V Output Current (A)
0.25
Fig. 5. The negative 5-V output of the circuit in Fig. 1 provides good
cross-regulation.
is only slightly larger than a comparable single-winding
inductor and with only a marginally higher cost. The best
circuit performance is realized with the lowest possible
winding resistance, since winding resistance degrades voltage
regulation as the load increases.
Output voltage waveforms at powerup are shown in
Fig. 4. The negative 5 V is able to track the positive 5 V
precisely. This is due to the inductor’s secondary-winding
voltage being clamped to the positive 5-V output voltage on
a pulse-by-pulse basis. Regardless of the positive 5-V output
voltage, the negative voltage will track it within the small
voltage drops associated with Q2B, Q1 and the winding
resistance of L1.
In Fig. 5, measurements on the negative 5-V output
reveal its load regulation. The curves highlight the variation
in the negative 5-V voltage as it is loaded, with each curve
at a different positive 5-V load. There is ±1% variation in
voltage regulation over loading and another ±1% variation
from cross-loading the positive 5-V output. This results
in a total output variation of ±2%. The losses associated
with the additional circuit are quite low. The additional
output achieves 95% efficiency alone under most loading
conditions.
PETech
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Power Electronics Technology February 2006
26
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