Improving Topological ATPG with Symbolic Techniques
F. Corno, P. Prinetto, M. Sonza Reorda
U. Gläser, H.T. Vierhaus
Politecnico di Torino
Dipartimento di Automatica e Informatica
Torino, Italy
GMD
SET
Sankt-Augustin, Germany
Abstract*
This paper presents a new approach to Automatic
Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to
deal with very large circuits, but often fail when highly
sequential subnetworks are found. On the other hand,
symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or
medium circuits, no matter their sequential complexity.
A state-of-the-art structural ATPG is extended by
identifying some critical areas in the circuit and resorting to symbolic techniques when such areas need to be
considered. Experimental results prove that the combined approach considerably enhances fault coverage
while reducing CPU time when compared to a purely
topological approach.
1. Introduction
Automated Test Pattern Generation (ATPG) for
digital circuits is a major research topic. As far as the
single stuck-at fault model is considered, efficient algorithms have been devised for combinational networks. Large sequential circuits, however, still constitute a problem. None of the methods proposed can fully
handle all the real-world circuits test engineers have to
deal with, since they either definitely fail or generate
sequences with very low fault coverage. Several types
of approaches have been suggested:
• topological: extension of the algorithms for
combinational circuits to sequential ones, by
adopting the Huffman Model [NiPa91]
* This work has been partially supported by Esprit Project 6575
“ATSEC” and by the Italian National Research Council “Progetto
Speciale Specifica ad alto Livello e Verifica Formale di Sistemi Digitali”.
Contact address: Paolo Prinetto, Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129
Torino (Italy), e-mail Paolo.Prinetto@polito.it
[KSLe93]. Topological algorithms are often
adopted for scan-based architectures, where the
test generation task is eased by means of partial
or full scan;
• simulation-based: employment of the results
provided by a fault simulator [ACAg88]
[HIHH92]. Methods based on Genetic Algorithms [SSAb92] [RHSP94] [PRSR94] also belong to this group;
• symbolic: use of the knowledge of both the output and the next-state functions of the circuit
[CHSo93].
The most widely used ATPGs usually adopt topological techniques, which suffice for circuits of moderate size and complexity. However, when highly sequential circuits are considered, the backtracking activity inherent in the search space exploration reduces
the quality of tests considerably because of the increased number of aborted faults.
On the other hand, the last years have seen the development of new techniques for Boolean functions
representation and manipulation, based on Binary
Decision Diagrams (BDDs) [Brya86]. It is now possible to efficiently handle complex functions with a large
number of input variables, keeping the memory and
CPU time requirements acceptable [BRBr90]. Some
attempts were made to apply symbolic techniques to
test pattern generation, but their applicability seems to
be limited to some tens of flip flops [CHSo93] or to
supply approximate results [CCQu94a] [CCQu94b].
In this paper an approach is presented, which combines the ability of topological techniques to deal with
large circuits with the fast and exact answers that symbolic techniques provide when applied to small but
complex sub-circuits. Some highly sequential macros
are identified in the circuit, and their Boolean functions
are computed; macros are kept small enough to be
easily handled with BDDs.
The choice of the macros may be a critical problem
for reaching the maximum efficiency. When a topdown design methodology is adopted, then macros can
correspond to embedded Finite State Machines or random control logic, whose boundaries are clearly defined by the designer. On the other hand, if no highlevel information is available, a structural analysis is
performed on the circuit netlist to identify the portions
where flip-flops are more strongly nested in feedback
loops. However, the focus of this paper is on test pattern generation and not on the choice of the macros.
In our approach two ATPG kernels are used. The
topological one, acting as a master, tries to generate
test patterns as usual. However, when faced with a hard
task on a macro, it calls a symbolic procedure to compute an answer efficiently. The adopted topological
algorithm is FOGBUSTER, a state-of-the-art structural
ATPG [WGVi94]. FOGBUSTER is known to be faster
than HITEC [NiPa91] on the average.
Experimental results show that the number of backtracks of FOGBUSTER is greatly reduced, leading to a
consistent reduction in CPU time and to an increased
fault coverage due to the reduced number of aborted
faults.
This paper is structured as follows: Section 2 outlines the adopted topological algorithm, mainly derived
from the FOGBUSTER approach. Section 3 introduces
symbolic techniques, showing how elementary tasks
such as propagation, justification and state traversal
can be computed. Section 4 deals with the complex
tasks that symbolic procedures are able to compute. In
Section 5 some very preliminary experimental results
are presented, while Section 6 draws some conclusions.
2. FOGBUSTER test generation technique
In this section the different phases of FOGBUSTER
(FOrward propaGation Backward jUstification Sequential TEst geneRation) are described. The algorithm proceeds in three main phases of computation:
1. forward propagation phase
2. propagation justification phase
3. initialization phase.
In the first phase the fault is transported to at least
one primary output of the circuit. Efficient heuristics
for fault propagation are used in this phase, for instance unique sensitization [FuSh83] with detection of
dynamic dominators. In the second phase, the propagation path is justified, e.g., unjustified signals of the
first phase which are at the pseudo outputs of the circuit are justified. In the initialization phase the initial
state of the time frame of fault occurrence is confirmed,
e.g., a synchronizing sequence for this state is computed.
If a fault is hard to detect the computing time for
finding a test pattern for this fault is too large. To keep
the computing time low, the maximal number of backtracks for one fault can be limited by the user.
Therefore, after a test pattern for any fault is found,
fault simulation for all the not yet detected faults of the
test generation process is performed.
In Fig. 1 a simplified diagram of the FOGBUSTER
algorithm is shown. After selecting a fault and executing fault injection, the combinational FAN is started to
compute a combinational test pattern for this fault. In
this part of test generation, combinational redundancies
can directly be identified. If a combinational test pattern is generated, the fault effect may be visible at least
at one primary output. In this case the initialization
phase is directly started from here on. Otherwise the
fault effect must be visible at least at one pseudo output, e.g., at one storing element of the circuit, and one
or more time frames are needed to propagate this fault
effect to a primary output. Then the forward propagation phase has to be entered.
In the forward propagation phase a pattern sequence
is computed to make the fault effect visible at a primary
output of the circuit. For each time frame in the fault
propagation, the FAN-algorithm for a multi-fault
model is called. A multi-fault model is needed in the
FAN-algorithm because the good machine and the
faulty machine are possibly different at least at one
pseudo input and at the fault location. If there is no
path for fault propagation to a primary output for the
computed combinational pattern, e.g., the combinational pattern is redundant, a backtrack has to be performed to the combinational FAN-algorithm. If a pattern sequence propagating the fault effect to a primary
output is found, the propagation phase terminates, and
the propagation justification phase is started.
In the propagation justification phase, all bound
lines [FuSh83] of the sequential elements that are still
unjustified from the propagation phase are justified. If
justification is not possible, a backtrack to the first
phase, the propagation phase, is performed. Otherwise
after termination the initialization phase is started.
In the initialization phase a synchronizing sequence
to the initial state (the state required after the propagation justification process) with respect to fault location
is computed. This means that the good and the bad
machine both must justify a required state. On termination of this third phase, a test pattern sequence for
the selected fault is found. If there is no synchronizing
sequence for the initial state, a backtrack to the propagation justification phase or to the combinational FAN
algorithm (if no propagation was required after the
combinational FAN execution) is performed.
The initialization phase of the FOGBUSTERalgorithm is equal to the BACK-algorithm after
reaching the fault location. The main differences in
FOGBUSTER are the D-propagation through the time
frames and the propagation justification.
states can be computed by repeating the computation of the image of a set of states under the
state transition function, according to the equation: χs, i+1(y) = ∃x ∃s [χs, i(s) χδ(s, x, y)].
These equations can be efficiently computed when
all the functions are represented by their respective
BDD. The basic operations described above can thus be
used by the topological algorithm whenever deemed
useful.
4. Integrated Approach
3. Symbolic Techniques
Symbolic Techniques can be used to reason about
the behavior of the circuit, independently of its topology. In this case, the circuit is modeled as a Finite State
Machine, and is represented by the Boolean function δ
computing the next state y from the current state s and
the current input x, y = δ(s, x), and by the function λ
computing the output z starting from the same information, z = λ(s, x). Such functions are extracted from
the circuit netlist, and completely describe its input/output behavior.
The adopted technique is quite standard, and resorts
to the adoption of characteristic functions to represent
sets of inputs, sets of states, and state transition functions [BCMD90]. Characteristic functions are Boolean
functions, therefore they can be represented by BDDs
and efficiently operated on by specialized Boolean
operators.
The characteristic function χδ of the state transition
function y = δ(s, x) is a compact representation of all
the triples (s, x, y) satisfying function δ: the characteristic function χδ(s, x, y) takes the value 1 for all the
triples (s′, x′, y′) such that y′ = δ(s′, x′).
Using such a representation, it is extremely easy to
extract the information items that are needed during
ATPG:
• Propagation: given a set of input constraints and
state constraints, compute the corresponding
permitted output values. If the sets of allowed
inputs and states are modeled by their characteristic functions, χx(x) and χs(s), respectively, then
the characteristic function of the output set of
values is χy(y) = ∃x ∃s [χx(x) χs(s) χδ(s, x, y)].
• Justification: the same idea applies when trying
to compute input constraint starting from output
knowledge: χx(x) = ∃y ∃s [χy(y) χs(s) χδ(s, x, y)].
• State traversal: knowing which states are accessible to a circuit is essential to avoid trying to
justify an invalid state. The set of reachable
The following assumptions are made:
• the circuit is a synchronous sequential one, and
test pattern generation starts from the reset state
• some macro structures are identified in the circuit, which will be handled by symbolic algorithms
• the topological ATPG acts as a master, generating test patterns in the usual way. Whenever
FOGBUSTER reaches a macro boundary, it can
ask the symbolic ATPG library for some piece of
information
• the fault to be tested for is always located outside
the macro block, so that symbolic techniques
need to deal with the behavior of the fault-free
machine, only.
The remainder of this section analyzes the possible
pieces of information that are useful to FOGBUSTER
and convenient to compute by symbolic means. The
following four procedures have been recognized as
convenient:
1. extraction of invalid state and output configurations of a sequential macro, to be used as constraints by FOGBUSTER during the preprocessing phase:
− this procedure computes the state configurations and output configurations that may
never appear in a sequential macro if the circuit is started from the reset state;
− some constraints on the inputs of the macro,
deduced by a structural analysis, may also be
specified;
− the computed forbidden state configurations
are used to limit FOGBUSTER search space;
2. evaluation of output values of combinational
macros:
− the task of evaluating a macro is defined as
the computation of output values corresponding to a given input combination. The only
difficulties are the correct interpretation of X
and U logic values;
3. justification of a set of output values across
combinational macros:
− this procedure computes the input configurations necessary to justify a given logic value
of some outputs of the macro, subject to some
input constraints;
− inputs to the procedure are input and output
constraints, and an output goal, i.e., a logical
value that must be justified on an output wire;
− if the imposed constraints are compatible,
then all the satisfying assignments that justify
the requested goal are computed;
4. determination of necessary conditions for the
propagation of a D/D’ across a combinational
macro:
− forward propagation of a D/D’ through a
macro is complex since there are potentially
many possible input combinations which fit
the requirements;
− the procedure computes necessary conditions
only, i.e., propagation conditions that must be
fulfilled by any propagating cube;
− FOGBUSTER limits its search to assignments
satisfying the computed necessary conditions.
5. Experimental results
To validate the effectiveness of the above approach,
a prototype implementation has been developed and
some experiments were run on a sample of ISCAS’89
benchmarks on a Sun Sparc 10. Circuit names ending
with an “o” refer to optimized, less redundant, versions
of the circuits. As an initial evaluation, only procedure
1 (extraction of invalid state and output configurations)
has been implemented.
Tab. 1 reports test pattern generation results when
the basic FOGBUSTER algorithm is run, while data
collected by running the integrated structural-symbolic
approach are gathered in Tab. 2. In these tables,
“Backtracks” is the number of backtracks made by
FOGBUSTER, “Redundant” is the number of faults
proven untestable, and “Aborted” is the number of
faults for which the backtrack limit was reached. Results of the ATPG are measured by the test pattern
length and its efficiency, i.e., the number of faults either tested or tagged as untestable. CPU times for test
pattern generation (column “TPG”) and fault simulation (column “FS”) are also reported.
By comparing the two tables, one can argue that:
• the adoption of symbolic techniques is able to
greatly reduce the number of aborted faults, virtually enhancing to 100% the fault efficiency;
• the reduced backtracking activity positively reflects on CPU times.
This sample of experimental data is able to prove
the feasibility of the approach, since we were able to
improve the results of the highly sophisticated
FOGBUSTER test pattern generator both in terms of
fault coverage and CPU time.
6. Conclusions
This paper presents a new approach to test pattern
generation for sequential circuits, integrating topological search algorithms with symbolic manipulations
based on Binary Decision Diagrams. The rationale
behind the integration is that topological techniques are
able to deal with large circuits, provided their sequential depth is reduced, while symbolic techniques can
cope with highly sequential circuits of small and medium size.
In the integrated approach we propose, some critical
areas of a circuits are identified, being hard to test with
the topological approach: in those areas, symbolic
manipulations are used to justify and propagate logic
values and to prune the search space by computing
invalid configurations.
Experimental evidence proves that the integrated
approach is superior to the purely topological one both
in terms of fault coverage and CPU times. Current
work aims at implementing and integrating the remaining symbolic procedures, and at addressing large circuits by clever selection of the macros.
Acknowledgments
The authors wish to thank Alessandro Bocchino for
development and implementation of the symbolic manipulation procedures.
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[WGVi94]
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on Computer Design, 1994
redundant fault
select next fault
apply FAN to
combinational logic
redundant
result?
success
fault at
output?
no
redundant
forward
propagation
phase
yes
result?
success
propagation
justification
phase
redundant
redundant
result?
s ucces s
result?
initialization
phase
success
test found
Figure 1: FOGBUSTER algorithm
Circuit
s27
s208
s298
s298o
s344
s349
s382o
s386
s386o
s400o
s420
s444o
s510
s641
s713
s832o
s953o
Total
Backtracks
2
1218
14926
11082
691
1015
786266
2098
2226
1394124
11135
1178905
6056
68
17
1151823
476940
5038592
Redundant
0
124
44
16
16
20
4
75
24
29
445
18
1
152
242
15
7
1232
Aborted
0
0
12
1
0
0
33
1
0
150
3
116
0
0
0
58
26
400
Test
pattern
length
17
236
385
169
100
123
732
273
242
195
244
241
452
221
230
406
387
4653
Fault
efficiency
[%]
100.0
100.0
95.8
99.5
100.0
100.0
88.1
99.7
100.0
44.0
99.3
59.7
100.0
100.0
100.0
90.3
97.2
92.56
TPG [s]
FS [s]
0
27
263
37
7
10
8168
65
18
13473
212
10373
150
3
3
4430
3894
41133
0
2
3
0
1
1
8
3
1
5
10
3
7
3
5
4
9
65
Fault
efficiency
[%]
100.0
100.0
100.0
100.0
100.0
100.0
88.5
100.0
100.0
94.6
99.3
90.4
100.0
100.0
100.0
89.3
97.6
97.63
TPG [s]
FS [s]
4
29
51
6
11
13
4608
15
10
1964
199
3431
118
15
15
4441
3932
18862
0
2
2
0
1
1
8
3
1
9
8
8
6
3
4
5
11
72
Table 1: FOGBUSTER results
Circuit
s27
s208
s298
s298o
s344
s349
s382o
s386
s386o
s400o
s420
s444o
s510
s641
s713
s832o
s953o
Total
Backtracks
2
1216
1185
887
129
176
371976
737
2028
185000
11115
341349
5502
68
17
1182281
793585
2897253
Redundant
0
124
60
17
16
20
5
76
24
17
445
16
1
152
242
15
16
1246
Aborted
0
0
0
0
0
0
28
0
0
13
3
26
0
0
0
64
22
156
Test
pattern
length
17
236
413
172
100
123
729
273
208
1535
244
803
431
221
230
396
393
6524
Table 2: results for the Integrated Approach