Reprinted from
REGULAR PAPER
Comparative Study of Tunneling Field-Effect Transistors
and Metal–Oxide–Semiconductor Field-Effect Transistors
Woo Young Choi
Jpn. J. Appl. Phys. 49 (2010) 04DJ12
# 2010 The Japan Society of Applied Physics
Person-to-person distribution (up to 10 persons) by the author only. Not permitted for publication for institutional repositories or on personal Web sites.
Japanese Journal of Applied Physics 49 (2010) 04DJ12
REGULAR PAPER
Comparative Study of Tunneling Field-Effect Transistors
and Metal–Oxide–Semiconductor Field-Effect Transistors
Woo Young Choi
Department of Electronic Engineering, Sogang University, 1 Shinsu-dong, Mapo-gu, Seoul 121-742, Korea
Received September 24, 2009; revised November 10, 2009; accepted November 24, 2009; published online April 20, 2010
Electrical characteristics of tunneling field-effect transistors (FETs) have been compared with those of metal–oxide–semiconductor FETs
(MOSFETs) in terms of subthreshold swing (SS), on/off current ratio, off current and on current. According to simulation results, tunneling FETs
have advantages over MOSFETs for low-power consumption: smaller SS below 60 mV/dec at room temperature, lower off current, higher on/off
current ratio and better immunity to short channel effects. However, low on current of tunneling FETs is problematic for reasonable circuit
performance. In this paper, in order to boost on current, strain-induced low bandgap substrate has been considered. It is observed that on current
of tunneling FETs can be comparable with that of MOSFETs as more strain is applied. The tunneling FET can be thought of as a promising
alternative to the MOSFET for low-power application. # 2010 The Japan Society of Applied Physics
DOI: 10.1143/JJAP.49.04DJ12
1.
Introduction
Tunneling FET
For the past 50 years, performance improvement through
scaling-down has been the most important issue among
device researchers. However, recent global energy crisis and
burgeoning demand of portable devices make power
reduction more important. Thus, low-power consumption
becomes one of the most important requirements in semiconductor industry. The most efficient way to reduce power
consumption is to reduce operating voltage (VDD ) on which
both standby and dynamic power consumptions are dependent. However, in the case of metal–oxide–semiconductor
field-effect transistors (MOSFETs), it is difficult to achieve
sub-1-V VDD . It is because the subthreshold swing (SS) of
MOSFETs has a physical limitation of 60 mV/dec at room
temperature. As long as carriers are injected from the source
by thermionic emission mechanism, the only way to achieve
sub-60-mV/dec SS is to lower temperature, which is not
applicable to consumer electronics. Hence, recently, there
have been many studies1–6) on novel devices for sub-60mV/dec SS at room temperature. Among them, we have
focused on the tunneling FET3) whose basic structure is a
gated p–i–n diode as shown in Fig. 1(a). For comparison,
Fig. 1(b) shows the structure of the MOSFET. The structural
difference between the tunneling FET and MOSFET leads
to different operation mechanism. Figures 1(c) and 1(d)
show the off-state band diagrams of tunneling FETs and
MOSFETs, respectively. Since the p–i–n diode is reverse
biased and band-to-band tunneling barrier is thick, only little
amount of output current flows in the case of tunneling
FETs. MOSFETs have off condition due to high energy
barrier between the channel and source. However, in on
state, tunneling FETs utilize band-to-band tunneling as a
source carrier injection method while MOSFETs adopt
thermionic emission as shown in Figs. 1(e) and 1(f). Thus,
the tunneling FET has extremely small off current and no
lower physical limit in the SS value. Experimentally, we
have confirmed that the tunneling FET can have sub-60mV/dec SS at room temperature in previous research.3)
However, the feasibility of the tunneling FET as an
alternative to the MOSFET has not been fully discussed.
In this paper, the characteristics of tunneling FETs will be
compared with that of MOSFETs in terms of SS, on/off
E-mail address: wchoi@sogang.ac.kr
LG
N+ doped
Poly-Si
Oxide
SOI or SSOI
BOX
MOSFET
Gate
LG
P+ doped
N+ doped
Poly-Si
Oxide
tox
tSOI
SOI or SSOI
BOX
(a)
(b)
Off state
Off state
Tunneling (X)
Thermionic
emission (X)
(d)
(c)
EC
Tunneling (O)
electron
EC
EV
E
electron C
EV
On state
Gate
N+ doped
EV
EC
electron
EV
(e)
On state
electron
Thermionic
emission (O)
(f)
Fig. 1. (Color online) (a) Schematic of tunneling FET. Drain and source
region have the opposite type of dopants. (b) Schematic of MOSFET.
Drain and source region have the same type of dopants. (c) Band
diagram of tunneling FET in off state. Band-to-band tunneling is not
allowed due to thick tunneling barrier. (d) Band diagram of MOSFET in off
state. Carriers are rarely injected from the source due to high energy
barrier between source and channel. (e) Band diagram of tunneling FET
in on state. Band-to-band tunneling is allowed due to thin tunneling
barrier. (f) Band diagram of MOSFET in on state. Carriers are injected
from the source due to low energy barrier between source and channel.
current ratio, on current and off current by using simulation
results.
2.
Simulation and Results
Two-dimensional simulation has been performed by ATLAS
simulator.7) A nonlocal band-to-band tunneling model has
been utilized in device simulation. Simulation parameters
were carefully adjusted referring to our previous work.3)
Figures 1(a) and 1(b) show the simulated structures of the
tunneling FET and MOSFET, respectively. Abrupt source/
drain doping profile has been assumed in this work. TFETs
and MOSFETs have a source/drain doping concentration of
1020 cm3 and a channel doping concentration of 1014 cm3 .
The channel is p-type doped in both kinds of devices. For
04DJ12-1
# 2010 The Japan Society of Applied Physics
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Jpn. J. Appl. Phys. 49 (2010) 04DJ12
W. Y. Choi
1012
10
10 -3
400
10 8
Solid: Tunneling FET
Open: MOSFET
10 7
10 6
0.1
10 5
10 1
10 0
2
3
4
5
300
10 -5
10 -14
10 -15
Solid: Tunneling FET
Open: MOSFET
LG = 70 nm
tSOI = 70 nm
SOI substrate
200
100
10 -16
0
10 -17
10 -1
0.01
10 -4
2
6
On current (µA/µm)
10 9
Off current (A/µm)
1010
LG = 70 nm
t = 70 nm
1 SOI
SOI substrate
On/off current ratio
SS (V/dec)
1011
3
4
5
tox (nm)
tox (nm)
(a)
(b)
6
0.01
10
20
350
300
250
200
150
100
50
On current (µA/µm)
0.1
10 -3
SOI substrate
10 -4
L = 70 nm
10 -5 G
10 -6 t ox = 2 nm
10 -7
10 -8
10 -9
10 -10
10 -11
10 -12
10 -13
10 -14
10 -15
10 -16
10 20 30 40
Solid: Tunneling FET
Open: MOSFET
1
1012
1011
1010
10 9
L G = 70 nm
10 8
t ox = 2 nm
10 7
SOI substrate 10 6
Solid: Tunneling FET 10 5
Open: MOSFET
10 4
10 3
10 2
10 1
10 0
10 -1
30 40 50 60 70
Off current (A/µm)
SS (V/dec)
10
On/off current ratio
Fig. 2. (Color online) (a) SS and on/off current ratio of tunneling FETs and MOSFETs with variation of tox . (b) Off and on current of tunneling FETs
and MOSFETs with variation of tox .
0
50
tSOI (nm)
tSOI (nm)
(a)
(b)
60
70
Fig. 3. (Color online) (a) SS and on/off current ratio of tunneling FETs and MOSFETs with variation of tSOI . (b) Off and on current of tunneling FETs
and MOSFETs with variation of tSOI .
fair comparison between the MOSFET and tunneling FET,
each device shares the same structure and device parameters
except that either source or drain of tunneling FETs is p-type
doped. Thus, it should be noted that the design of MOSFETs
presented in this work has not been fully optimized. It means
that performance parameters of MOSFETs in this work
cannot match International Technology Roadmap for Semiconductors (ITRS) data.8) We observed four parameters such
as SS, on/off current ratio, on current and off current as a
function of the gate oxide thickness (tox ), the silicon-oninsulator (SOI) layer thickness (tSOI ) and strain. All four
parameters were extracted when the drain voltage is 1 V. The
off current was defined as the minimal drain current while
the on current was defined as the drain current when the gate
voltage increased by 1 V from its off state value. The gate
length (LG ) was fixed at 70 nm.
Figure 2 shows the dependence of the four parameters on
tox . As tox decreases, the SS value is observed to become
smaller both in tunneling FETs and MOSFETs. It is because
the SS value is determined by two factors: the coupling
between the gate voltage and channel potential and the
influence of the drain voltage on the tunneling or channel
barrier. As tox is scaled down, the channel potential becomes
more closely coupled to the gate voltage and tunneling or
channel barrier are less influenced by the drain voltage,
which decreases SS value. Thus, the SS value of tunneling
FETs becomes less than 60 mV/dec when tox is around
2 nm.3) On the contrary, MOSFETs show high SS value due
to severe short channel effects. Also, the on/off current ratio
of tunneling FETs is observed to increase more abruptly than
that of MOSFETs as tox becomes smaller. It is because the
on current increases faster and off current increases slower in
tunneling FETs than in MOSFETs for smaller tox as shown
in Fig. 2(b). Firstly, on current is related to short channel
effects. As tox is scaled down to 2 nm, short channel effects
are relieved in tunneling FETs while MOSFETs still remain
in the punch-through mode. It is confirmed by the SS values
in Fig. 2(a). Thus, as tox decreases, on current of tunneling
FETs increases more abruptly than that of MOSFETs.
Secondly, off current of tunneling FETs is generally less
influenced by tox since it stems from p–i–n junction leakage.
However, tunneling FETs have another source of off current:
ambipolar behavior.9) Since the source and the drain have
opposite kinds of dopants in tunneling FETs, when the gate
voltage is low, both n- and p-channel behavior occur at the
same time, which leads to gradual off current increase with
oxide downscaling.
Figure 3 shows the dependence of the four parameters on
tSOI . It seems that the performance of MOSFETs is improved
faster than that of tunneling FETs as tSOI decreases. It is
because short channel effects become less severe as tSOI
decreases in the case of MOSFETs. Since MOSFETs
04DJ12-2
# 2010 The Japan Society of Applied Physics
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Jpn. J. Appl. Phys. 49 (2010) 04DJ12
10 -8
1010
10 -9
10 8
0.1
0.01
10 7
10 6
LG = 70 nm
tox = 2 nm
tSOI = 20 nm
0.0
0.1
10 5
0.3
10 -11
250
200
10 -12
150
10 -13
100
10 -14
50
10 -15
0
10 -16
10 4
0.2
10 -10
/
10 9
300
Solid: Tunneling FET
Open: MOSFET
LG = 70 nm
tox = 2 nm
tSOI = 20 nm
0.0
0.4
On current (µA/µm)
1011
Off current (A/µm)
Solid: Tunneling FET
Open: MOSFET
On/off current ratio
SS (V/dec)
1
W. Y. Choi
0.1
0.2
0.3
0.4
x of Si1-xGex
x of Si1-xGex
(a)
(b)
Fig. 4. (Color online) (a) SS and on/off current ratio of tunneling FETs and MOSFETs with variation of strain. (b) Off and on current of tunneling FETs
and MOSFETs with variation of strain.
become less influenced by short channel effects, SS
decreases and on/off current ratio increases abruptly as
tSOI decreases. On the contrary, short channel effects have
already been suppressed even when tSOI is larger than LG
in the case of tunneling FETs. As shown in Fig. 3(a),
regardless of tSOI , tunneling FETs exhibit lower SS and
higher on/off current ratio than MOSFETs in spite of its low
on current. Additionally, it should be noted that on current
of tunneling FETs exceeds that of MOSFETs when
tSOI ¼ 30 nm. It is related to the definition of on current in
this work. Since on current is defined as the drain current
when the gate voltage increases by 1 V from its minimal
value, on current is smaller than maximal attainable drain
current. If threshold voltages are adjusted at the sacrifice of
off current, on current of MOSFETs will be higher than that
of tunneling FETs even when tSOI is less than 30 nm.
Although the tunneling FET exhibits an extremely low SS
and off current value which are beneficial to low-power
consumption, in terms of circuit performance, its on current
should also be improved. However, even the maximal
attainable drain of tunneling FETs is still two orders of
magnitude smaller than that of MOSFETs.3) Since low on
current of tunneling FETs stems from the source carrier
injection mechanism: band-to-band tunneling, lower bandgap substrate such as strained SOI (SSOI)10) can be
introduced for further improvement of on current. In an
SSOI wafer, strained silicon layer is grown epitaxially on
Si1x Gex layer. As germanium concentration increases in
the Si1x Gex layer, more strain is applied to the silicon
layer, which leads to lower bandgap energy.11) In order to
compare the electrical characteristics of tunneling FETs and
MOSFETs as a function of strain level, we increase x of
Si1x Gex from 0 to 0.4, which means higher strain and lower
bandgap energy. Figure 4 shows the dependence of the four
parameters on x of Si1x Gex . Although more stain is applied
to the SSOI substrate, the SS values of tunneling FETs and
MOSFETs remain almost the same. However, as strain
increases, the on current of tunneling FETs increases more
abruptly than that of MOSFETs at the sacrifice of on/off
current ratio. It should be noted again that on currents of
tunneling FETs and MOSFETs were extracted when the gate
voltage increased by 1 V from its minimal value. When the
gate voltage increases further, the on current of MOSFETs
will be higher than that of tunneling FETs. Since the off
current increases more abruptly than the on current as a
function of strain in the case of tunneling FETs, on/off
current ratio lowering is inevitable when high on current is
required.
3.
Conclusions
Comparative study of tunneling FETs and MOSFETs has
been performed in terms of SS, on/off current ratio, off
current and on current for low-power consumption. Tunneling FETs exhibit extremely small SS and off current and
good immunity to short channel effects compared with
MOSFETs. Although the on current of tunneling FETs is
lower than that of MOSFETs, it is observed that lower
bandgap substrate such as SSOI can boost the on current at
the sacrifice of on/off current ratio due to rapid off current
increase. It is expected that the tunneling FET can be a good
alternative to the MOSFET for low-power application.
Acknowledgments
This work was supported in part by the National Research
Foundation of Korea, funded by the Ministry of Education,
Science and Technology, under Grants 2009-0082439 and
2009-0084522 and in part by the Korea Sanhak Foundation
under a 2009 research grant.
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# 2010 The Japan Society of Applied Physics