S
G
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ELE6308
Microélectronique analogique et mixte
--- Switched-Capacitor Circuits --Mohamad Sawan, Professor
Kamal El-Sankary, Ph.D.
Laboratoire de neurotechnologies Polystim
http://www.cours.polymtl.ca/ele6308/
mohamad.sawan@polymtl.ca
M5418
Switched-Capacitor Circuits
Plan
I. Switch
 Ron
 Charges injection
 Clock feedthrough
I. Sample and hold
II. Switched-Capacitor Filters
 Integrators
 Signal flow-graph analysis
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ELE6308- Microélectronique analogique et mixte
On-Resistance of switch
In circuits it is necessary to “hold” the sampled signal for some period of time.
A simple Sample & Hold circuit is formed by a sampling switch followed by a
hold capacitor and an output buffer.
VDS/2 <<0
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ELE6308 - Microélectronique analogique et mixte
Charge Injection
The charges carried in a MOS channel when it is on is:
• The error for an NMOS switch appears as a negative “pedestal” at the output.
• This component is linearly related to Vin and VTn (body effect).
• Charges injected cause errors, such as DC Offset, Gain error, and Nonlinearity (Harmonic
distortion), the most important effect.
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ELE6308 - Microélectronique analogique et mixte
Clock Feedthrough
It is due to the overlap capacitance between gate-source and gate-drain. It is
independent of the input level and produces an offset voltage at the output
This component is smaller than that due to the channel charge and appear as an offset.
Trade-off between speed and precision.
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ELE6308 - Microélectronique analogique et mixte
Reduction of S&H Nonidealities
Dummy switch
• The charge injected by the main transistor
can be removed by means of a second
transistor.
• After Q1 turn off and Q2 turn on, the
channel charges deposited by the former on
Ch is absorbed by the later to create a
channel.
• If W2 is exactly ½ W1, then the charges will
cancel.
• Clock feedthrough is suppressed.
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ELE6308 - Microélectronique analogique et mixte
Reduction of S&H Nonidealities
CMOS Sampling Switch
• If PMOS and NMOS have
the same charge, charge
injection cancels out, but not
perfectly. Different turn-off
times due to finite slope of
the clock waveforms.
• Partial cancellation of the
channel charge is achieved,
but the cancellation is signal
dependent.
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Reduction of S&H Nonidealities
Fully Differential Sampling
The charge injection
appears as a commonmode disturbance.
only if Vi1=Vi2
The overall error is not
suppressed for differential
signals, but no offset and
only odd-order distortion.
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Reduction of S&H Nonidealities
Bottom Plate Sampling
• Switches M2A&B are opened
slightly earlier compared to
M1A&B
Injected charges by the
opening of M2A&B are constant
and will be eliminated when used
differentially
• Since bottom plate of C is
open when M1A&B are opened
 No charges injected can result.
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ELE6308 - Microélectronique analogique et mixte
Reduction of S&H Nonidealities
S&H based on bottom-plate sampling
• At the instant of sampling,
some of the charges stored in
sampling switch S1 are dumped
onto C.
• With "Bottom Plate Sampling", charges injection comes only from S1 and is
independent of vIN
– Only a DC offset is added to the input signal
– This DC offset can be removed with a differential architecture.
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ELE6308 - Microélectronique analogique et mixte
Switched-Capacitor Resistor
• C1 charged to V1 and then V2 during each clk period :
• If periodic, the equivalent average current is :
• For equivalent resistor circuit
• Equating two equations, we have
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ELE6308 - Microélectronique analogique et mixte
Switched-Capacitor Resistor
Example: the equivalent resistance of a 5 pF capacitance sampled at a
clock frequency of 100 kHz is:
• Note that a very large equivalent resistance of 2 MΩ can be realized;
• Requires only 2 transistors, a clock and a relatively small capacitance;
• In a typical CMOS process, such a large resistor would normally require a
huge amount of silicon area.
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ELE6308 - Microélectronique analogique et mixte
Accuracy of SC Circuits
The transfer function of this simple circuit is,
is the time constant of the circuit and determines the accuracy.
Continuous Time Accuracy
;
Discrete Time Accuracy
;
The above is the primary reason for the success of switched capacitor CMOS circuits.
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ELE6308 - Microélectronique analogique et mixte
Basic Building Blocks of SCC
Non-Overlapping Clocks
• Both clocks are never ON at same time
• Needed to ensure charges are not inadvertently lost.
• Integer values occur at end of φ 1.
• End of φ 2 is 1/2 off integer value.
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Basic Building Blocks of SCC
Capacitors
• Substantial parasitics with large bottom plate capacitance (20 percent of C1)
• MiM capacitor has the smallest bottom plate capacitors (<5%).
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ELE6308 - Microélectronique analogique et mixte
Parasitic-Sensitive Integrator
• Start by looking at an integrator which is affected by parasitic capacitances
• Want to find output voltage at end of φ 1 in relation to input sampled at end of
φ 1.
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ELE6308 - Microélectronique analogique et mixte
Parasitic-Sensitive Integrator
• At end of φ 2
• But would like to know the output at end of φ 1
• Leading to
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Parasitic-Sensitive Integrator
Modify above to write
Taking z-transform and re-arranging leads to
Notes:
• Gain-coefficient is determined by a ratio of two capacitance values.
• Ratios of capacitors can be set VERY accurately in an IC (0.1%)
• Leads to accurate transfer functions.
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Typical Waveforms
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ELE6308 - Microélectronique analogique et mixte
Low Frequency Behavior
This equation
can be re-written as
To find frequency response,
recall
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Low Frequency Behavior
• Above is exact but when ω T << 1 (i.e., at low freq)
• Thus, the transfer function is same as a continuous-time integrator
having a gain constant of
which is a function of the integrator capacitors ratio and clock frequency
only.
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ELE6308 - Microélectronique analogique et mixte
Parasitic Capacitance Effects
• Accounting for parasitic capacitances, we have
• Cp3 has little effect since it is connected to virtual gnd
• Cp4 has little effect since it is driven by output
• Cp2 has little effect since it is connected to physical gnd
• Thus, gain coefficient is not well controlled and partially non-linear (due
to Cp1 being non-linear).
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Parasitic-Insensitive Integrators
• By using 2 extra switches, integrator can be made insensitive to
parasitic capacitances
— more accurate transfer-functions
— better linearity (since non-linear capacitances unimportant).
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ELE6308 - Microélectronique analogique et mixte
Parasitic-Insensitive Integrators
• Same analysis as before except that C1 is
switched in polarity before discharging into C2 .
• A positive integrator (rather than negative as
before).
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ELE6308 - Microélectronique analogique et mixte
Parasitic-Insensitive Integrators
• Cp3 has little effect since it is connected to virtual gnd
• Cp4 has little effect since it is driven by output
• Cp2 has little effect since it is either connected to virtual gnd or physical gnd.
• Cp1 is continuously being charged to and discharged to ground.
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ELE6308 - Microélectronique analogique et mixte
Parasitic-Insensitive Inverting
Integrator
• Present output depends on present
input (delay-free)
• Delay-free integrator has negative gain
while delaying integrator has positive gain.
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Signal-Flow-Graph Analysis
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ELE6308 - Microélectronique analogique et mixte
Signal-Flow-Graph Analysis:
Example
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ELE6308 - Microélectronique analogique et mixte
Signal-Flow-Graph Analysis:
Example
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ELE6308 - Microélectronique analogique et mixte
Switch Sharing
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ELE6308 - Microélectronique analogique et mixte
Fully-Differential Filters
• Most modern SC filters are fully-differential
• Common-mode noise is rejected.
• Even order distortion terms cancel
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Fully-Differential Filters
• Note that fully-differential version is essentially two copies of singleended version, however area penalty not twice.
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