EE40 Lec 15
Logic Synthesis
and
S
Sequential
Logic C
Circuits
P f N
Prof.
Nathan
h Ch
Cheung
10/20/2009
Reading: Hambley Chapters 7.4-7.6
Karnaugh Maps: Read following before reading textbook
http://www.facstaff.bucknell.edu/mastascu/eLessonsHTML/Logic/Logic3.html
EE40 Fall 2009
Slide 1
Prof. Cheung
Synthesis of Logic Circuits
Suppose we are given a truth table for a logic function.
Is there a method to implement the logic function using
basic logic gates?
Answer: There are lots of ways, but one way is the
“
“sum
off products”
d t ” (SOP) method:
th d
1)) Write the sum of p
products expression
p
based on the
truth table for the logic function
2) Implement this expression using standard logic gates.
•
An alternative way is the “product of sums” (POS)
method.
EE40 Fall 2009
Slide 2
Prof. Cheung
Logic Synthesis Example: Adder
S1= carry, So=sum
A
0
0
0
0
1
1
1
1
Truth Table of Adding
Three Inputs :
A, B, and C
EE40 Fall 2009
Slide 3
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
S1 S0
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1
Prof. Cheung
Logic Synthesis Example: Adder
Input
A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
EE40 Fall 2009
C
0
1
0
1
0
1
0
1
Output
Sum-of-products method for S1
S1 S0
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1
1) Find rows where S1 is 1
2) Write down each product of
inputs which create a 1 (invert
logic variables that are 0 in that
row)
ABC
ABC
ABC
ABC
1) Sum all of the products
ABC+ ABC+ ABC+ ABC
2) Draw the logic circuit
Slide 4
Prof. Cheung
Logic Synthesis Example: Adder
ABC+ ABC+ ABC+ ABC
A
A
C
B
C
SOP Logic Circuit
B
C
A
B
A
B
C
EE40 Fall 2009
Slide 5
Prof. Cheung
Creating a Better Circuit
What makes a digital circuit better?
• Fewer number of gates
• Fewer inputs on each gate
– multi-input gates are slower
• Let’s see how we can simplify the sum-ofproducts expression for S1, to make a
better circuit…
– Use the Boolean algebra relations
EE40 Fall 2009
Slide 6
Prof. Cheung
Logic Synthesis Example: Adder
ABC + AB C + AB C + ABC
A
B
C
= ABC + AB C + AB( C + C)
= ABC + AB C + AB
A
C
B
A
B
SOP Simplification
Can we simplify this digital circuit further?
EE40 Fall 2009
Slide 7
Prof. Cheung
Logic Synthesis Example: Adder
A
B
Add in two
inversions
(signal stays the
same)
B
C
A
C
A
B
EE40 Fall 2009
Slide 8
Prof. Cheung
Logic Synthesis Example: Adder
A
B
This becomes a NAND
B
C
A
C
A
B
Apply DeMorgan’s
Theorem, i.e. “bubble
pushing”
hi ”
X + Y + Z = XYZ
EE40 Fall 2009
Slide 9
Prof. Cheung
NAND Gate Implementation
• De Morgan’s law tells us that
is the same as
• By definition,
is the same as
Æ All sum-of-products expressions can be implemented with only NAND gates.
EE40 Fall 2009
Slide 10
Prof. Cheung
Logic Synthesis Example: Adder
Output
Input
A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1
1
EE40 Fall 2009
C
0
1
0
1
0
1
0
1
S1 S0
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1
Product-of-sums method for S1
1) Find rows where S1 is 0
2) Write down each sum of inputs
which create a 0 (invert logic
variables that are 1 in that row)
( A + B + C) ( A + B + C )
( A + B + C) ( A + B + C)
3) Product of the sums
( A + B + C)( A + B + C )( A + B + C)( A + B + C)
4) Draw the logic circuit
Slide 11
Prof. Cheung
SOP or POS ?
The Boolean Expression
p
will appear
pp
shorter
• If the Truth table has less 1’s, SOP
• If the Truth Table has less 0
0’s
s, POS
• After Minimization, both methods should
give same results , unless there are “don’t
care” rows in the Truth Table.
EE40 Fall 2009
Slide 12
Prof. Cheung
Notations of Hambley Textbook
Sum of Products (SOP)
D = Σ m ( 0 , 2 ,6 ,7 )
Product of Sums ((POS))
D = Π M(1,3,4,5)
EE40 Fall 2009
Slide 13
Row #
0
1
2
3
4
5
6
7
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Prof. Cheung
D
1
0
1
0
0
0
1
1
Another Logic Synthesis Example: XOR
Sum of Products (SOP)
F = Σ m(1,2)
F = AB + AB
EE40 Fall 2009
A
B
F
0
0
0
0
1
1
1
0
1
1
1
0
Slide 14
Product of Sums (POS)
F = Π M(0,3)
F = ( A + B )( A + B )
Prof. Cheung
Karnaugh Maps
2-variable
Karnaugh Map
3-variable
Karnaugh Map
4-variable Karnaugh Map
* Arrows show example locations of logic PRODUCTS
EE40 Fall 2009
Slide 15
Prof. Cheung
Comments on Karnaugh Maps
•
•
Required reading
http://www.facstaff.bucknell.edu/mastascu/eLessonsHTM
L/Logic/Logic3 html
L/Logic/Logic3.html
•
You may find more details there than the textbook.
•
As the number of variables increases (say >4) it becomes
more difficult to see patterns
patterns, and computer methods
start to become more attractive.
•
EE40 will
ill focus
f
only
l on 3 variables
i bl and
d 4 variables
i bl
Karnaugh Maps
EE40 Fall 2009
Slide 16
Prof. Cheung
Comments on Karnaugh Maps
For a 4-variables map
1-cube: 1 square by itself
((⇒ logic
g p
product of 4 variables))
2-cube: 2 squares that have a
common edge
(⇒ logic product of 3 variables)
4-cube: 4 squares with common edges
(⇒ logic product of 2 variables)
8-cube: 8 squares with common edges
(⇒ logic product of 1 variable)
EE40 Fall 2009
Slide 17
Prof. Cheung
Comments on Karnaugh Maps
•
In locating cubes on a Karnaugh map, the map should be considered
to fold around from top to bottom, and from left to right.
– Squares on the right-hand side
are considered to be adjacent to
those on the left-hand
left hand side.
side
– Squares on the top of the map are
considered to be adjacent to those
on the bottom.
–
CD
00 01 11 10
00 1
Example:
p
The four squares in the
map corners form a 4-cube
AB
01
11
10 1
EE40 Fall 2009
Slide 18
1
1
Prof. Cheung
4-Variables Example
•
•
•
From Truth
F
T th Table
T bl and
d Sum
S
off Products
P d t
F=Σ m(1,3,4,5,7,10,12,13)
Converting the row numbers to binary yields 0001,0011,
0001 0011
0100 etc..
Place 1’s into the Karnaugh
g Map
F = A B C D + AD + B C
EE40 Fall 2009
Slide 19
Prof. Cheung
3-Variables Example: Adder
I
Input
t
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
EE40 Fall 2009
O t t Simplification of expression for S1:
Output
S1
0
0
0
1
0
1
1
1
S0
0
1
1
0
1
0
0
1
B
BC
A
0
1
00 01 11 10
0 0 1 0
0 1 1 1
C
BC
AC
AB
S1 = AB + BC + AC
Slide 20
Prof. Cheung
Miscellaneous Examples
EE40 Fall 2009
Slide 21
Prof. Cheung
3-Variable Exercise
EE40 Fall 2009
Slide 22
Prof. Cheung
4-Variable Exercise
EE40 Fall 2009
Slide 23
Prof. Cheung
Exercise with “Don’t Cares”
EE40 Fall 2009
Slide 24
Prof. Cheung
Sequential Logic Circuits
• Sequential logic circuits that possess memory
because their present output value depends on
previous
i
as wellll as presentt iinputt values.
l
EE40 Fall 2009
Slide 25
Prof. Cheung
Clock Signals
• Often, the operation of a sequential circuit is
synchronized by a clock signal :
vC(t)
positive-going edge
(leading edge)
VOH
0
TC
2TC
negative-going edge
(trailing edge)
time
• The clock signal regulates when the circuits
respond to new inputs
inputs, so that operations occur
in proper sequence.
• Sequential circuits that are regulated by a clock
signal are said to be synchronous.
EE40 Fall 2009
Slide 26
Prof. Cheung
Flip-Flops
• One of the basic building blocks for sequential
circuits is the flip-flop:
– A simple flip-flop can be constructed using two
inverters:
Q
Q
Two possible states:
Q = 1, Q = 0
Q = 0, Q = 1
* Circuit can remain in either state indefinitely
EE40 Fall 2009
Slide 27
Prof. Cheung
The S-R (“Set”-“Reset”) Flip-Flop
S Q
S-R Flip-Flop Symbol:
R Q
• Rule 1:
– If S = 0 and R = 0, Q does not change.
• Rule 2:
– If S = 0 and R = 1, then Q = 0
• Rule 3:
– If S = 1 and R = 0,
0 then Q = 1
• Rule 4:
– S = 1 and R = 1 should never occur.
EE40 Fall 2009
Slide 28
Prof. Cheung
Realization of the S-R Flip-Flop
S
Q
Q
R
EE40 Fall 2009
R
S
Qn
0
0
Qn-1
0
1
1
1
0
0
1
1
(not allowed)
Slide 29
Prof. Cheung
XOR and NAND Implementation
EE40 Fall 2009
Slide 30
Prof. Cheung
Exercise: Timing Diagram of SR flip-flop
R
S
Qn
0
0
Qn-1
0
1
1
1
0
0
1
1
((not allowed))
Q
EE40 Fall 2009
Slide 31
Prof. Cheung
Clocked S-R Flip-Flop
• Wh
When CK = 0,
0 disables
di bl th
the iinputs
t R and
dS
• When CK = 1, enables inputs R and S
EE40 Fall 2009
Slide 32
Prof. Cheung
The D (“Delay”) Flip-Flop
D
D Flip-Flop Symbol:
Q
CK Q
• The output terminals Q and Q behave just as in
the S-R flip-flop.
• Q changes
h
only
l when
h th
the clock
l k signal
i
l CK
makes a positive transition. CK D
Qn
EE40 Fall 2009
Slide 33
0
×
Qn-1
1
×
Qn-1
↑
0
0
↑
1
1
Prof. Cheung
D Flip-Flop Example (Timing Diagram)
CK
t
D
t
Q
t
EE40 Fall 2009
Slide 34
Prof. Cheung
Registers
• A register is an array of flip-flops that is used to
store or manipulate the bits of a digital word.
• Example: Serial-In,
Serial In Parallel-Out
Parallel Out Shift Register using D
Flipflops
Q0
Parallel outputs
Data input
Q1
Q2
D0 Q0
D1 Q1
D2 Q2
CK
CK
CK
Cl k iinputt
Clock
EE40 Fall 2009
Slide 35
Prof. Cheung
Shift Register
Timing Diagram
EE40 Fall 2009
Slide 36
Prof. Cheung
J-K Flip Flop
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Slide 37
Prof. Cheung
Ripple Counter
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Slide 38
Prof. Cheung
Conclusion (Logic Circuits)
• Complex combinational logic functions can be
achieved simply by interconnecting NAND gates
(or NOR gates).
• Logic gates can be interconnected to form flipflops.
• Interconnections of flip-flops form registers.
• A complex digital system such as a computer
consists of many gates, flip-flops, and registers.
Th
Thus,
logic
l i gates
t are the
th basic
b i building
b ildi bl
blocks
k
for complex digital systems.
EE40 Fall 2009
Slide 39
Prof. Cheung