Advancing the Analog Custom Design Interoperability Tom Quan 18th Synopsys EDA Interoperability Developers’ Forum, Santa Clara CA, November 9, 2006 AWR Product Solutions System Components Satellite 3G-Wireless WiMax UWB 802.11a,b,g.. Bluetooth xDSL Cable Optical Communications Subsystems Design Subsystem IP Component Libraries Microwave IC, Module & PCB Design Analog & RFIC Design Silicon SiGe/CMOS Foundry PDKs GaAs InP/InGaP/… Foundry PDKs Circuit Components LNAs Mixers Amps Transceivers QAM QPSK Laser Drivers & Detectors PLLs Synthesizers Filters CDRs MUXs AWR – Tom Quan – EDA Interoperability Developers’ Forum 2 Interactive Design Environment (fully parametric with built-in statistical analysis & optimization) RF 3D Extractor Interactive DRC Assisted Place & Route IC/Package/PCB Layout Intelligent Net™ EM Simulator(s) HSPICE Simulator Aplac Simulators HB/Linear Simulator Visual System Sim Integrated Waveform Display & Analysis Design Capture C++, Visual Basic Scripting Environment AWR Solution Architecture System Libs & Process Design Kits (Si, SiGe, GaAs, InP) Integrated Database/Object-Oriented Data Model Unified Data Model & UI for All Phases of Design AWR – Tom Quan – EDA Interoperability Developers’ Forum 3 Data and Tool Interfaces Analog Office Design Flow Full Chip Integration With Digital Blocks System Models Silicon Foundry PDKs Full Chip Schematic Full Chip Layout Full Chip Extraction Current Design Schematics Layout LVS Netlist Post Layout Simulation Full Chip DRC/LVS RFIPs System Design/Sim VSS Design Entry AO Circuit Simulation HB/HSPICE/APLAC Circuit Simulator Spectre Block/Chip Layout AO Router Pulsic’s Lyric On-the-Fly Extraction AO Inductance Helic’s VeloceRF Net Extraction AO/Net-An EM Extraction CST, IE3D, Sonnet,.. DRC/LVS AO Interface DRC/LVS Calibre Tapeout Tapeout AWR – Tom Quan – EDA Interoperability Developers’ Forum 4 AWR Open Design Platform • Unified data model interoperable with OpenAccess – Support easy-to-use & highly interactive design environment – OA data model compliant – Clean interfaces with other OpenAccess compliant tools • Open API/Open Sockets – EM simulation/extraction – 7 tools plugged in today – Circuit simulation – 4 simulators plugged in today – Physical design – layout editor, auto P&R, and layout compaction plugged today – Physical verification – 2 DRC/LVS tools today • Open PDK – Standard Pcell development language – C++, Python, Tcl Open Platform Ù Interoperability AWR – Tom Quan – EDA Interoperability Developers’ Forum 5 AWR Interoperability System/T&M APLAC models Spectre/Matlab Verification Mentor Calibre ICED LVS/DRC Cadence Assura Design Capture Cadence Schematic I/F Cadence Open Access Mentor Boardstation EM Analysis & Extraction Circuit Simulation Sim Socket EMSight CST OEA Sonnet Zeland Optimal MEM Res Vector Fields APLAC HSPICE Spectre HyperLynx Layout PDKs GDSII <> Cadence/Synopsys OpenAccess <> Pulsic Mentor PCB Products TSMC, Jazz, Peregrine, IHP AWR – Tom Quan – EDA Interoperability Developers’ Forum AWR Company Confidential 6 RF Process Design Kit ¾Configurable passive & active components ¾Scalable active devices ¾Accurate RF non-linear device models ¾Symbols, models, layout generators, DRC/LVS rules ¾Temperature variations, corners • Active devices • NPN transistors for digital/high performance/high breakdown • RF and standard N- & P-channel MOSFETS • Junction varactor • MOS varactor • N+ P-well diode/P+ N-well diode • Passive devices • Metal-insulator-metal capacitor • Scalable octagonal inductor • N-well resistor with multiplicity for series/parallel connection • Polysilicon resistors with multiplicity for series connection • Diffusion resistors with multiplicity for series connection AWR – Tom Quan – EDA Interoperability Developers’ Forum SiGe NPN Inductor Varactor Resistor 7 PDK Interoperability Requirements • Design constraints – Electrical – Physical – Manufacturing • Simulation Models Symmet r y Di st ance bet ween i nduct i ve el ement s Pl acement of dummy el ement s Pl acement of pass capaci t or s P&R of guar d banc Common cent r oi d Pl acement of par i Tr . s Zi g zag pl acement of Rs Encl osed R, C and MOS I sol at i on of N-r egi on, Addi t i onal subst r at e f or MO – HSPICE, Spectre, others • Electrical – Schematic symbol – Naming conventions – Electrical/physical parameters • Physical – Parameterized Cells (Pcells) – DRC/LVS/LPE/DFM rules (from foundry) – GDS layer map (from foundry) AWR – Tom Quan – EDA Interoperability Developers’ Forum Gen:Bic35:SPIRAL ID=L1 NTURNS=2.5 W=5 um S=2 um IDia=50 um Gen:Bic35:npn1 ID=Q1 N=1 Imax=1.5 mA 1 4 2 Sub npn1 3 8 PCell on OpenAccess PyCell PCell SKill PCell Scripted TCL PCell Python PCell PyCell Library C++ PCell Compiled Skill Evaluator TCL Evaluator Python Evaluator Python Evaluator API OA PCell API OA PCell API OA PCell API OA PCell API OA PCell API OpenAccess API Reference OpenAccess Database • • Which approach used does not matter that much Pcells created using any of the approaches could be ported to any OA system – Compiled PCells will require compilation on each supported platform – Scripted PCells will only require the supporting plug-in to be compiled on each platform AWR – Tom Quan – EDA Interoperability Developers’ Forum 9 Steps to Ensure PDK Interoperability 1. Validating several sets of generic Pcells written in Python, C++ and Tcl on one OAcompliant design platform (AWR) 2. Validating one set of generic Pcells on different OA-compliant design platforms 3. Defining a common format for electrical and physical parameters 4. Defining a common format for design constraints 5. Validating a generic PDK on different OAcompliant design platforms AWR – Tom Quan – EDA Interoperability Developers’ Forum 10 Thank You! Tom Quan (tomq@appwave.com)