Laboratory Experiment #8: Arithmetic‐Logic Unit Modeling Ari Mahpour ECE 526 Lab Student ID #: 101146706 Table of Contents Purpose ....................................................................................... 3 Test Strategy ............................................................................... 4 Results ........................................................................................ 5 Conclusion .................................................................................. 5 Waveform Diagram .................................................................... 6 Purpose The purpose of this lab was to design and implement an arithmetic logic unit into a purposeful Verilog module. The arithmetic logic unit performs a series of calculations integral to the functionality of the central processing unit. Whether it be a simple math function of data storage, the arithmetic logic unit will perform it all. A three bit input, known as the operational code (opcode), triggers the operation based on a number. For example, an input of 101 will pass the data bus contents to the output. A total of eight opcodes can be used in the this particular arithmetic logic unit. Other inputs consist of a carry in bit, a clock, the accumulator eight bits), and the data itself (eight bits). In this implementation, a simple case statement did the job. It would treat each opcode as a case and perform whatever function that specific opcode designated. In addition, other one bit outputs had to be evaluated. These included a carry flag, overflow flag, sign flag, zero flag, and parity flag. After performing a function in the arithmetic logic unit, each of these one bit outputs would hold a value corresponding to the data that was processed (via the designated opcode). Test Strategy The test vectors in this laboratory experiment were targeted to test the functionality of the arithmetic logic unit and ensure that all of its functions performed correctly. In the test bench itself, a clock was generated and each operation was tested individually on the clock. The case statement is only evaluated at the positive edge of the clock therefore it was imperative that the timing of the simulations would run simultaneously. Rather than setting each function to run at every edge of the clock (i.e. 20 ns clock frequency), the clock would have a period of 2 nanoseconds and each function would be evaluated at every 10 nanoseconds. Throughout the process of running through each opcode, various outputs had to be observed such as the carry, overflow, sign, zero, and parity flag. Each one of the one‐bit outputs could have had potentially different values at each individual operational states, therefore, each bit was observed using the “$monitor” function in the test bench. Also, documented int eh test bench are points where certain flags are anticipated to turn on (in which results will be discussed in the next section). Results The results for the test strategy came out to be a success. When performing each function, the necessary flags had turned on (or off) and each function was performed without any issues. Wehtehr it was simply passing data, adding values, or running each bit of a data input through a primitive gate, each function proved to be a success. For this laboratory exercise, both the LOG file and the output waveform do justice to what the outputs should look like. The output value (known in the module as alu_out) was displayed as “OUT” simply for aesthetic purposes. Just as the data loaded was in hexadecimal form, so too the output was represented in the hexadecimal form. Both the output LOG file and waveform vector file can be viewed at the end of this laboratory report. Conclusion In the laboratory experiment we explored a very important concept that was clearly applied to the computer architecture world. The concept of case statements proved to work quite well in this particular implementation of the arithmetic logic unit. No other behavioral design (at least that in which we learned thus far) would have been as efficient and worked as well as the case statement. In the hardware implementation, this can work as a switcher, more commonly known as a multiplexer. As seen in many circuit descriptions, multiplexers are an essential part of any logic circuit. Without them, digital design would be much more difficult. After learning about the arithmetic logic unit we move onto the next lab which is the final piece to the digital design of the central processing unit. Page 1 of 1
Test Bench
Ari Mahpour
Baseline = 0
Cursor = 0
Baseline = 0
Cursor-Baseline = 0
TimeA = 0
0
ZF
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CF
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OF
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PF
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accum[7:0]
'hxx
alu_out[7:0]
'hxx
c_in
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clock
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data[7:0]
'hxx
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FF
opcode[2:0]
'hx
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Printed on Sun Nov 15 02:10:57 PM PST 2009
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Printed by SimVision from Cadence Design Systems, Inc.
tb_alu.v
/**********************************************************************************
***
***
*** ECE 526 L Experiment #8
Ari Mahpour, Fall, 2009 ***
***
***
*** Arithmetic-Logic Unit Modeling
***
***
***
***********************************************************************************
*** Filename: tb_alu.v
Created by Ari Mahpour, 11/03/2009 ***
***
***
***********************************************************************************
*** This is a test bench for the ALU module.
***
***********************************************************************************/
`timescale 1ns / 100ps
module tb_alu();
reg [2:0] opcode;
reg [7:0] accum, data;
reg c_in;
wire [7:0] alu_out;
wire CF, OF, SF, ZF, PF;
reg clock;
alu UUT(alu_out, CF, OF, SF, ZF, PF, opcode, accum, data, c_in, clock);
initial
begin
$write("
");
$display("Time OUT
CF
OF
SF
$monitor("%d
%h
%b
%b
%b
$time, alu_out, CF, OF, SF, ZF, PF);
end
initial
begin
clock = 1'b0;
forever #1 clock =
end
ZF
%b
PF");
%b",
~clock;
initial
begin
// Opcode 000
//Flag ZF
#10 accum = 8'h00; opcode = 3'b000; data = 8'hFF;
//Unflag ZF and flag sign bit
//PF should not set
#10 accum = 8'hA1;
// Opcode 001
//Flag ZF
#10 accum = 8'h00; opcode = 3'b001;
//Unflag ZF and flag sign and parity
#10 accum = 8'hA1;
// Opcode
#10 accum
#10 accum
#10 accum
010
= 8'h11; data = 8'h22; c_in = 1'b0; opcode = 3'b010;
= 8'hFF; data = 8'h00; c_in = 1'b1;
= 8'hFF; data = 8'hFF; c_in = 1'b0;
//Opcode 011
#10 accum = 8'hFF; data = 8'hAA; opcode = 3'b011;
#10 accum = 8'h00; data = 8'h01;
Page 1
tb_alu.v
//Opcode 100
#10 accum = 8'hAA; data = 8'hAA; opcode = 3'b100;
#10 accum = 8'hEE; data = 8'hED;
//Opcode 101
#10 data = 8'h07; opcode = 3'b101;
#10 data = 8'hA1;
// Opcode 110
//ZF should flag
#10 accum = 8'h00; opcode = 3'b110;
//Unflag ZF and flag sign bit
//PF should not set
#10 accum = 8'hA1;
// Opcode 111
//ZF should flag
#10 accum = 8'h00; opcode = 3'b111;
//Unflag ZF and flag sign bit
//PF should not set
#10 accum = 8'hA1;
#10 $finish;
end
endmodule
Page 2
alu.v
/**********************************************************************************
***
***
*** ECE 526 L Experiment #8
Ari Mahpour, Fall, 2009 ***
***
***
*** Arithmetic-Logic Unit Modeling
***
***
***
***********************************************************************************
*** Filename: alu.v
Created by Ari Mahpour, 11/03/2009 ***
***
***
***********************************************************************************
*** This module represents an ALU module.
***
***********************************************************************************/
`timescale 1ns / 100ps
module alu(alu_out, CF, OF, SF, ZF, PF, opcode, accum, data, c_in, clock);
output reg [7:0] alu_out;
output reg CF, OF, SF, ZF, PF;
input [2:0] opcode;
input [7:0] accum, data;
input c_in, clock;
always @ (posedge clock)
begin
case (opcode)
3'b000:
begin
alu_out = accum;
CF = 1'b0;
OF = 1'b0;
PF = 1'b0;
ZF = ~(|alu_out);
SF = alu_out[7];
end
3'b001:
begin
alu_out = accum;
PF = ^alu_out;
CF = 1'b0;
OF = 1'b0;
ZF = ~(|alu_out);
SF = alu_out[7];
end
3'b010:
begin
alu_out = accum + data + c_in;
if((accum & data) | (accum & c_in) | (data & c_in))
CF = 1'b1;
else
CF = CF;
PF = ^alu_out;
ZF = ~(|alu_out);
SF = alu_out[7];
if((accum[7] == data[7]) != alu_out[7])
OF = 1'b1;
end
3'b011:
begin
alu_out = accum & data;
Page 1
PF
OF
ZF
CF
SF
=
=
=
=
=
alu.v
^ alu_out;
1'b0;
~(|alu_out);
1'b0;
alu_out[7];
end
3'b100:
begin
alu_out = accum ^ data;
PF = ^ alu_out;
CF = 0;
OF = 0;
ZF = ~(|alu_out);
SF = alu_out[7];
end
3'b101:
begin
alu_out = data;
PF = 1'b0;
ZF = ~(|alu_out);
CF = 1'b0;
OF = 1'b0;
SF = alu_out[7];
end
3'b110:
begin
alu_out = accum;
PF = 1'b0;
OF = 1'b0;
CF = 1'b0;
ZF = ~(|alu_out);
SF = alu_out[7];
end
3'b111:
begin
alu_out = accum;
PF = 1'b0;
CF = 1'b0;
OF = 1'b0;
ZF = ~(|alu_out);
SF = alu_out[7];
end
default:
begin
alu_out = 8'b0;
PF = 1'b0;
CF = 1'b0;
OF = 1'b0;
ZF = 1'b0;
SF = 1'b0;
end
endcase
end
endmodule
Page 2
ncverilog: 08.20-s012: (c) Copyright 1995-2009 Cadence Design Systems,
Inc.
TOOL: ncverilog
08.20-s012: Started on Nov 15, 2009 at 17:15:09 PST
ncverilog
tb_alu.v
alu.v
Recompiling... reason: file './tb_alu.v' is newer than expected.
expected: Sun Nov 15 12:08:16 2009
actual:
Sun Nov 15 17:15:01 2009
file: tb_alu.v
module worklib.tb_alu:v
errors: 0, warnings: 0
file: alu.v
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.tb_alu:v <0x10afc97e>
streams:
4, words: 8561
Loading native compiled code:
.................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules:
2
2
Registers:
11
11
Scalar wires:
7
Vectored wires:
4
Always blocks:
1
1
Initial blocks:
3
3
Simulation timescale: 100ps
Writing initial simulation snapshot: worklib.tb_alu:v
Loading snapshot worklib.tb_alu:v .................... Done
ncsim> source /opt/cadence/IUS0820/tools/inca/files/ncsimrc
ncsim> run
Time OUT
CF
OF
SF
ZF
PF
0
xx
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1
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a1
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a1
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0
1
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1
51
33
0
1
0
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0
61
00
1
1
0
1
0
71
fe
1
1
1
0
1
81
aa
0
0
1
0
0
91
00
0
0
0
1
0
111
03
0
0
0
0
0
121
07
0
0
0
0
0
131
a1
0
0
1
0
0
141
00
0
0
0
1
0
151
a1
0
0
1
0
0
161
00
0
0
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1
0
171
a1
0
0
1
0
0
Simulation complete via $finish(1) at time 180 NS + 0
./tb_alu.v:87
#10 $finish;
ncsim> exit
TOOL: ncverilog
08.20-s012: Exiting on Nov 15, 2009 at 17:15:11 PST
(total: 00:00:02)
I hereby attest that this lab report is entirely my own work. I have not copied either code or text from anyone, nor have I allowed or will allow anyone to copy my work. Name (printed): ______________________________________ Name (signed): ______________________________________ Date: ___________________