A fractionally spaced linear receive equalizer with voltageto-time conversion
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Citation
Song, Sanquan, Byungsub Kim, and Vladimir Stojanovic. “A
fractionally spaced linear receive equalizer with voltage-to-time
conversion.” VLSI Circuits, 2009 Symposium on. 2009. 222-223.
©2009 IEEE.
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http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5205338
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Institute of Electrical and Electronics Engineers
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Wed May 25 21:43:36 EDT 2016
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http://hdl.handle.net/1721.1/60403
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A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion
Sanquan Song, Byungsub Kim, Vladimir Stojanović
Massachusetts Institute of Technology, 77 Mass Ave, RM38#266, Cambridge, MA 02139, USA
sanquan@mit.edu, byungsub@mit.edu, vlada@mit.edu
Abstract
Based on voltage-to-time conversion technique, a
pseudo-differential two-way-interleaved adaptive linear
receive equalizer with two 2x-oversampled feed-forward taps
has been designed in a 90 nm CMOS process. It integrates
equalization and phase interpolation functions into one unit to
simultaneously address inter-symbol-interference (ISI)
cancellation and phase synchronization in a link receiver. It
operates at 4 Gbps with 8 mW power consumption, and
linearity of 4.3 effective bits at 1.2 V supply.
Keywords: fractionally spaced receiver equalizer
Introduction
Intersymbol-interference (ISI) is becoming an increasingly
severe issue as target data rates increase in link applications,
challenging both the equalization and synchronization
sub-systems. Traditionally, adaptation loops in these two
sub-systems derive the error information from different
performance metrics (voltage errors at data sampling points
and error information at edge crossings). This discrepancy
results in sub-optimal link performance due to the interaction
of the two loops, especially in situations where received
signals are significantly asymmetrical and distorted by ISI
[1,2] (e.g. loop-unrolled decision-feedback equalizers).
Fractionally spaced equalizers enable controlled ISI
reduction at arbitrary sampling phase with a single adaptation
loop [3]. In this paper we describe an implementation of a two
2x oversampled feed-forward taps receiver equalizer structure.
Apart from oversampling speed challenges, implementation of
linear receiver equalizers has been a difficult problem due to
process mismatch and speed-power-nonlinearity trade-offs in
current-mode implementations in scaled, low-supply voltage
CMOS processes [4].
Architecture
To overcome these issues with good energy-efficiency, and
achieve 4~5 bit linearity required by the adaptive algorithm
the FSE design is based on voltage-to-time and
time-to-voltage conversion techniques [5]. Due to the process
speed limitation, half-rate time interleaving technique is also
applied, Fig. 1. Four sampling phases (Φ1- Φ4) with 25% duty
cycle are generated locally from Φ and Φ_ and another pair of
quadrature clocks. A voltage-to-time (V2T) block converts the
sampled signal into a delayed digital signal, transferring the
sampled information into time-domain. All four V2T
converters are followed by a time-to-voltage (T2V) stage to
realize summing, subtraction and multiplication.
Equalizer tap weights are implemented as two
programmable reference currents I1, I2 biasing T2V blocks.
Two slicers with tunable thresholds are added to sense the
signs of the input signal and output error of the FSE,
respectively, and enable tap weight adaptation with external
adaptive engine.
Implementation
A. V2T Converter
The V2T converter is shown in Fig. 2. When clock Φ_ is
low, nodes VS+/VS- are pre-charged to VDD. Simultaneously,
the sampling capacitors CS+/CS- track the input signals. The
following edge of Φ_ pulls the sampled voltages on nodes
VX+/VX- down by the same amount so that they are lower than
the threshold voltage at the initial state. Afterwards, two
identical currents Icharge+/- charge VX+/VX- respectively. The
nodes VX+/VX- will reach the threshold of N+/- at different
times and trigger two pairs of edges (E1r+/- and E1f+/-). To
shorten the decision time, P+/P- provide positive feedback,
improving the design speed by roughly 30%, for target time
dynamic range. The timing Δt between E1r+/E1f+ and E1r-/E1fis proportional to the differential input Vin1.
B. T2V Converter
The T2V converter operation is shown in Fig. 3, with
waveforms for I2=0 for simplicity. When Φ_ is low, output
nodes VO+/VO- are pre-charged to VDD. After the rising edge
of Φ_, nodes VO+/VO- are discharged with current I1 since
E1f+/E1f- are high and E1r+/E1r- are low. After the arrival of
E1f+/E1r+ edges, the discharge current by M1+ switches from
Vo+ to Vo-. Therefore, the discharge current of VO+ becomes
zero and that of VO- is doubled. Thus, the difference between
VO+ and VO- increases from zero till the arrival of E1f-/E1redges. Afterwards, the current by M1- is rerouted to VO+ and
the discharge currents for both are I1 again, and VO+/- decrease
with the same slope until the falling edge of Φ_. The voltage
output ΔVO is proportional to Vdiff,in1xI1 and Vdiff,in2xI2,
implementing the multiplication and summing operations.
Changing the sign multiplexer control will realize a
subtraction. T2V integrator has significantly improved
linearity over the traditional GmC stage since its inputs are
always full swing signals.
Measurements
The design is fabricated in a 90 nm CMOS process. The
chip layout is shown in Fig. 4, with additional support blocks
like scan chain and high-speed data snapshots to enable link
tuning and in-situ performance characterization. The FSE
receiver area is 65 µm x 130 µm.
At 4 Gbps rate, tuning the tap weights guarantees a flat open
eye within +/-5% for any delay between data and clock,
compared to the eyes visible by symbol-spaced slicers, Fig. 5b.
Due to larger than predicted parasitic capacitance at the VX
node in the V2T converter, the design exhibits about 2x
attenuation at VO with respect to the input signal, Fig. 5a, but
achieves target linearity of 4.3 effective bits with monotonic
gain in tap weights, Fig. 6.
Conclusion
Leveraging the speed of advanced digital processes, a
voltage-to-time conversion techniques provide an effective
way to overcome the linearity issues in high-speed link receive
filters and enable the implementation of fractionally-spaced
filters that simultaneously address the phase synchronization
and equalization tasks with good energy-efficiency.
The authors thank Jim Wieser, Jerry Socci, Ali Djabbari,
Hsinho Wu and Mounir Bohsali of National Semiconductor
and Fred Chen of MIT for the fruitful discussion and support
and FCRP Interconnect Focus Center and Trusted Foundry for
design fabrication.
References
[1] John F. Bulzacchelli et al, "A 10-Gb/s 5-Tap DFE/4-Tap FFE
Transceiver in 90-nm CMOS Technology," JSSCC, vol. 41, no.
12, Dec. 2006
[2] V. Stojanovic et al, "Autonomous dual-mode (PAM2/4) serial
link transceiver with adaptive equalization and data recovery,"
JSSCC, vol. 40, no. 4, Apr. 2005.
[3] E. A. Lee and D. G. Messerschmitt, Digital Communication,
Kluwer Academic Press, 1994.
[4] J.E. Jaussi et al, "8-Gb/s source-synchronous I/O link with
adaptive receiver equalization, offset cancellation, and clock
de-skew," JSSCC, vol. 40, no. 1, Jan. 2005.
[5] L. Brooks, H.-S. Lee, " A Zero-Crossing-Based 8-bit 200 MS/s
Pipelined ADC ", JSSCC, Dec. 2007
Feed-forward Blocks
Sampling Blocks
S/H & V2T
(Φs = Φ1)
S/H & V2T
(Φs = Φ2)
T2V
Sgn(err)
N+ N-
V1x-
Φ_
CS-
Φ_
Φ
Arbitrary delay
D0
D1
Φ_
Φ2
V1x+/V1x-
Vth ~= 300mV
V1s+/V1sE1r+/E1f+
E1r-/E1f-
Φ_
I2
Vo+ Vo-
I1
E1f+
E2f+
E2r-
E1r-
E1r+
E2r+
E2f-
SnapShot
E1f-
To the other
branch
M1+
M2-
M2+
M1-
SnapShot
Adaptive
Blocks
Φ_
SnapShot
S/H & V2T
(Φs = Φ3)
Φ
S/H & V2T
(Φs = Φ3)
E1r+/E1f+
ScanChain
T2V
αO
S/H & V2T
(Φs = Φ4)
Δt1
~b2k+1 SnapShot
E1r-/E1f-
Odd
Branch
ScanChain
Φ
ΔVo
Vo+/Vo+
Scan Out
S/H & V2T
(Φs = Φ4)
arbitrary
D0
D1
Data
I1 & I2
αE
D2
Fig. 3 Schematic and time diagram of T2V converter when I1> 0 and
I2 = 0. M1+, M1-, M2+ and M2- are shared by even/odd branches.
D3
Φ
Φ_
αO
Φ1
Φ2
+α/-α
Gen
Adaptive
Engine
Vin- IchargeΦ2
Φ_
P-
Φ
Data
Even
Branch
Vref_in
Vref_err
Φ_
Off Chip
Scan Chain
Φ3
Φ4
1mm
Sgn(Vin) Sgn(err) bk
Fig. 1 Block diagram of 2-tap 2xoversampled two-way time
interleaved architecture. Scan-chain and snapshot are applied for
in-situ link characterization.
0.14x0.115mm
Vin
Adaptive
Blocks
(36umx9um)
Sample
CLK
GEN
1mm
400
CLK
8 V2T
Cells
(54umx32
um)
(a) FSE Input Eye Openning @4Gbps
Scan Chain
Samplers and
Latches
(22umx32um)
Vo
Scan Chain
mV
300
Fig. 4 Die photo and chip floor plan.
200
250
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
(b) FSE Output Eye Openning @4Gbps
400
mV
300
I1 = 0
I2 = 15.5u
FSE output
I1 = 30.0u eye openning
I2 = 0
single-tap output
eye openning
I1 = 20.0u
I2 = 4.5u
200
FSE Differential Output (mV)
100
0
0
200
I1 = 16.5u, I2 = 0
I1 = 23.3u, I2 = 0
I1 = 55.5u, I2 = 0
150
100
50
100
0
0
0.2
0.4
E1f-
Ctrl from
Scan Chain
Vref_err
I1 & I2
Sgn(Vin)
Vin-
V1s-
P+
V1x+
CS+
ScanChain
S/H & V2T
(Φs = Φ2)
Vin+
Icharge+ Vin+
Φ2
Sign
Mux
Fig. 2 Schematic and time diagram of V2T converter
ScanChain
~b2k
αE
V1s+
Φ_
Scan In
ScanChain
Φ_
E1f+
Ctrl from
Scan Chain
E1r-
Φ_
Δt1
Scan Blocks
CONF
Φ_
Φ_
Sign
Mux
2 T2V Cells
(36umx6m)
S/H & V2T
(Φs = Φ1)
E1r+
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Delay between Data and CLK (Data Cycle - UI)
Fig. 5 Input (a), and FSE output (b) eye opening vs. sampling phase.
0
0
100
200
300
FSE Differential Input (mV)
Fig. 6 Linearity of the FSE for different tap weights.
400